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radeon/r200: fix bogus assert/scissor wrt width/height 2048 

This addresses one issue raised in bug #51658 discovered by Eugene St Leger.
The assert is bogus since there's no problem with texture width/height being
2048 (the width/height programmed is width/height minus one).
OTOH though the programmed size for scissor rect should be width/height
minus one too otherwise bad things may happen (as it is inclusive, and there's
not enough bits for more than a value of 2047).
This commit is contained in:
Roland Scheidegger 2012-07-27 04:03:45 +02:00
parent 6574fe3c4a
commit 5b88a2a22d
2 changed files with 8 additions and 8 deletions
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8
src/mesa/drivers/dri/r200/r200_blit.c
View File

@ -108,8 +108,8 @@ static void inline emit_tx_setup(struct r200_context *r200,
uint32_t txformat = R200_TXFORMAT_NON_POWER2;
BATCH_LOCALS(&r200->radeon);
assert(width <= 2047);
assert(height <= 2047);
assert(width <= 2048);
assert(height <= 2048);
assert(offset % 32 == 0);
/* XXX others? BE/LE? */
@ -341,8 +341,8 @@ static inline void emit_cb_setup(struct r200_context *r200,
OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0);
OUT_BATCH_REGVAL(R200_RE_CNTL, 0);
OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
(height << RADEON_RE_HEIGHT_SHIFT)));
OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) |
((height - 1) << RADEON_RE_HEIGHT_SHIFT)));
OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);

8
src/mesa/drivers/dri/radeon/radeon_blit.c
View File

@ -102,8 +102,8 @@ static void inline emit_tx_setup(struct r100_context *r100,
uint32_t txformat = RADEON_TXFORMAT_NON_POWER2;
BATCH_LOCALS(&r100->radeon);
assert(width <= 2047);
assert(height <= 2047);
assert(width <= 2048);
assert(height <= 2048);
assert(offset % 32 == 0);
/* XXX others? BE/LE? */
@ -216,8 +216,8 @@ static inline void emit_cb_setup(struct r100_context *r100,
BEGIN_BATCH_NO_AUTOSTATE(18);
OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
(height << RADEON_RE_HEIGHT_SHIFT)));
OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) |
((height - 1) << RADEON_RE_HEIGHT_SHIFT)));
OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);