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radv, ac, aco: Use indices 0-2 of gs_vtx_offset argument array on GFX9+. 

Previously, indices 0, 2, 4 were used.
This worked, but it was somewhat unintuitive.
This commit changes it to use indices 0, 1, 2 instead, which
makes the code easier to understand.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12511>
This commit is contained in:
Timur Kristóf 2021-08-24 08:20:32 +02:00 committed by Marge Bot
parent 18962b94d3
commit 5b7446d74c
6 changed files with 11 additions and 10 deletions
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4
src/amd/common/ac_nir_lower_esgs_io_to_mem.c
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@ -169,8 +169,8 @@ gs_per_vertex_input_vertex_offset_gfx9(nir_builder *b, nir_src *vertex_src)
{
if (nir_src_is_const(*vertex_src)) {
unsigned vertex = nir_src_as_uint(*vertex_src);
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u * 2u),
nir_imm_int(b, (vertex % 2u) * 16u), nir_imm_int(b, 16u));
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u),
nir_imm_int(b, (vertex & 1u) * 16u), nir_imm_int(b, 16u));
}
nir_ssa_def *vertex_offset = nir_build_load_gs_vertex_offset_amd(b, .base = 0);

5
src/amd/common/ac_nir_lower_ngg.c
View File

@ -289,9 +289,8 @@ emit_pack_ngg_prim_exp_arg(nir_builder *b, unsigned num_vertices_per_primitives,
static nir_ssa_def *
ngg_input_primitive_vertex_index(nir_builder *b, unsigned vertex)
{
/* TODO: This is RADV specific. We'll need to refactor RADV and/or RadeonSI to match. */
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u * 2u),
nir_imm_int(b, (vertex % 2u) * 16u), nir_imm_int(b, 16u));
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u),
nir_imm_int(b, (vertex & 1u) * 16u), nir_imm_int(b, 16u));
}
static nir_ssa_def *

2
src/amd/common/ac_shader_args.h
View File

@ -107,7 +107,7 @@ struct ac_shader_args {
struct ac_arg es2gs_offset; /* separate legacy ES */
struct ac_arg gs2vs_offset; /* legacy GS */
struct ac_arg gs_wave_id; /* legacy GS */
struct ac_arg gs_vtx_offset[6]; /* separate legacy GS */
struct ac_arg gs_vtx_offset[6]; /* GFX6-8: [0-5], GFX9+: [0-2] packed */
struct ac_arg gs_prim_id;
struct ac_arg gs_invocation_id;

2
src/amd/compiler/aco_instruction_selection.cpp
View File

@ -8901,7 +8901,9 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
break;
}
case nir_intrinsic_load_gs_vertex_offset_amd: {
/* GFX6-8 uses 6 separate args, while GFX9+ packs these into only 3 args. */
unsigned b = nir_intrinsic_base(instr);
assert(b <= (ctx->program->chip_class >= GFX9 ? 2 : 5));
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
get_arg(ctx, ctx->args->ac.gs_vtx_offset[b]));
break;

4
src/amd/vulkan/radv_nir_to_llvm.c
View File

@ -2097,7 +2097,7 @@ handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
LLVMValueRef vtxindex[] = {
ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[0]), 0, 16),
ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[0]), 16, 16),
ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[2]), 0, 16),
ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[1]), 0, 16),
};
/* Determine the number of vertices per primitive. */
@ -2940,7 +2940,7 @@ prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
if (merged) {
for (int i = 5; i >= 0; --i) {
ctx->gs_vtx_offset[i] = ac_unpack_param(
&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[i & ~1]), (i & 1) * 16, 16);
&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[i / 2]), (i & 1) * 16, 16);
}
ctx->gs_wave_id =

4
src/amd/vulkan/radv_shader_args.c
View File

@ -637,10 +637,10 @@ radv_declare_shader_args(struct radv_shader_args *args, gl_shader_stage stage,
}
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]);
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]);
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[1]);
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_prim_id);
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_invocation_id);
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[4]);
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]);
if (previous_stage == MESA_SHADER_VERTEX) {
declare_vs_input_vgprs(args);