radeonsi: stop using TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
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@ -462,8 +462,9 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
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}
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if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
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nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
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/* post_depth_coverage implies early_fragment_tests */
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info->base.fs.early_fragment_tests |= info->base.fs.post_depth_coverage;
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info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
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if (nir->info.fs.pixel_center_integer) {
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@ -3354,7 +3354,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
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/* The set of PS invocations is always order invariant,
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* except when early Z/S tests are requested. */
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if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.writes_memory &&
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sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
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sctx->ps_shader.cso->info.base.fs.early_fragment_tests &&
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!dsa_order_invariant.pass_set)
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return false;
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@ -2773,39 +2773,41 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
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break;
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}
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/* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
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*
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* | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
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* --|-----------|------------|------------|--------------------|-------------------|-------------
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* 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
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* 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
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* 2 | false | true | n/a | LateZ | 1 | 0
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* 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
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* 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
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*
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* In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
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* In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
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*
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* Don't use ReZ without profiling !!!
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*
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* ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
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* shaders.
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*/
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if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
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/* Cases 3, 4. */
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sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
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S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
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S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
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} else if (sel->info.writes_memory) {
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/* Case 2. */
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sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
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} else {
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/* Case 1. */
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sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
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}
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if (sel->info.stage == MESA_SHADER_FRAGMENT) {
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/* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
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*
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* | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
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* --|-----------|------------|------------|--------------------|-------------------|-------------
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* 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
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* 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
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* 2 | false | true | n/a | LateZ | 1 | 0
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* 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
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* 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
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*
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* In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
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* In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
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*
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* Don't use ReZ without profiling !!!
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*
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* ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
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* shaders.
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*/
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if (sel->info.base.fs.early_fragment_tests) {
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/* Cases 3, 4. */
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sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
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S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
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S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
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} else if (sel->info.writes_memory) {
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/* Case 2. */
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sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
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} else {
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/* Case 1. */
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sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
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}
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if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
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sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
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if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
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sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
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}
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(void)simple_mtx_init(&sel->mutex, mtx_plain);
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@ -3055,8 +3057,8 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
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if (sctx->screen->has_out_of_order_rast &&
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(!old_sel || old_sel->info.writes_memory != sel->info.writes_memory ||
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old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
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sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
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old_sel->info.base.fs.early_fragment_tests !=
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sel->info.base.fs.early_fragment_tests))
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si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
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}
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si_set_active_descriptors_for_shader(sctx, sel);
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