freedreno/a3xx: rework vinterp/vpsrepl
Make the interpolation / point-sprite replacement mode setup deal with varying packing. In a later commit, we switch to packing just the varying components that are actually used by the frag shader, so we won't be able to assume everything is vec4's aligned to vec4. Which would highly confuse the previous vinterp/vpsrepl logic. Signed-off-by: Rob Clark <robclark@freedesktop.org>
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@ -387,23 +387,27 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
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/* figure out VARYING_INTERP / FLAT_SHAD register values: */
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for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
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/* NOTE: varyings are packed, so if compmask is 0xb
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* then first, third, and fourth component occupy
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* three consecutive varying slots:
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*/
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unsigned compmask = fp->inputs[j].compmask;
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/* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
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* instead.. rather than -8 everywhere else..
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*/
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uint32_t inloc = fp->inputs[j].inloc - 8;
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/* currently assuming varyings aligned to 4 (not
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* packed):
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*/
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debug_assert((inloc % 4) == 0);
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if ((fp->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
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(fp->inputs[j].rasterflat && emit->rasterflat)) {
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uint32_t loc = inloc;
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for (i = 0; i < 4; i++, loc++) {
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vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
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flatshade[loc / 32] |= 1 << (loc % 32);
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for (i = 0; i < 4; i++) {
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if (compmask & (1 << i)) {
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vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
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flatshade[loc / 32] |= 1 << (loc % 32);
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loc++;
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}
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}
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}
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@ -416,10 +420,31 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
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* interpolation bits for .zw such that they become .01
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*/
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if (emit->sprite_coord_enable & texmask) {
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vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
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<< ((inloc % 16) * 2);
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vinterp[(inloc + 2) / 16] |= 2 << (((inloc + 2) % 16) * 2);
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vinterp[(inloc + 3) / 16] |= 3 << (((inloc + 3) % 16) * 2);
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/* mask is two 2-bit fields, where:
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* '01' -> S
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* '10' -> T
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* '11' -> 1 - T (flip mode)
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*/
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unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
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uint32_t loc = inloc;
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if (compmask & 0x1) {
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vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
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loc++;
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}
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if (compmask & 0x2) {
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vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
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loc++;
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}
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if (compmask & 0x4) {
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/* .z <- 0.0f */
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vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
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loc++;
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}
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if (compmask & 0x8) {
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/* .w <- 1.0f */
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vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
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loc++;
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}
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}
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}
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}
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