pan/midgard: Fix REGISTER_OFFSET

r27 isn't the special one, usually.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig 2019-08-01 14:06:02 -07:00
parent c908772ee4
commit 5a572f4b55
2 changed files with 2 additions and 3 deletions

View File

@ -170,8 +170,7 @@ quadword_size(int tag)
#define REGISTER_UNUSED 24 #define REGISTER_UNUSED 24
#define REGISTER_CONSTANT 26 #define REGISTER_CONSTANT 26
#define REGISTER_VARYING_BASE 26 #define REGISTER_LDST_BASE 26
#define REGISTER_OFFSET 27
#define REGISTER_TEXTURE_BASE 28 #define REGISTER_TEXTURE_BASE 28
#define REGISTER_SELECT 31 #define REGISTER_SELECT 31

View File

@ -662,7 +662,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
.ssa_args = { .ssa_args = {
.src0 = SSA_UNUSED_1, .src0 = SSA_UNUSED_1,
.src1 = offset, .src1 = offset,
.dest = SSA_FIXED_REGISTER(REGISTER_OFFSET), .dest = SSA_FIXED_REGISTER(REGISTER_LDST_BASE + 1),
}, },
.alu = { .alu = {
.op = midgard_alu_op_imov, .op = midgard_alu_op_imov,