freedreno/a3xx/compiler: scheduling/legalize fixes
It seems the write-after-read hazard that applies to texture fetch instructions, also applies to sfu instructions. Also, cat5/cat6 instructions do not have a (ss) bit, so in these cases we need to insert a dummy nop instruction with (ss) bit set. Signed-off-by: Rob Clark <robclark@freedesktop.org>
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@ -48,6 +48,11 @@ static void dump_instr_name(struct ir3_dump_ctx *ctx,
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fprintf(ctx->f, "%03u: ", instr->depth);
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}
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if (instr->flags & IR3_INSTR_SY)
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fprintf(ctx->f, "(sy)");
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if (instr->flags & IR3_INSTR_SS)
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fprintf(ctx->f, "(ss)");
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if (is_meta(instr)) {
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switch(instr->opc) {
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case OPC_META_PHI:
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@ -526,18 +526,41 @@ static void legalize(struct ir3_ra_ctx *ctx, struct ir3_block *block)
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}
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}
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/* cat5+ does not have an (ss) bit, if needed we need to
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* insert a nop to carry the sync flag. Would be kinda
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* clever if we were aware of this during scheduling, but
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* this should be a pretty rare case:
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*/
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if ((n->flags & IR3_INSTR_SS) && (n->category >= 5)) {
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struct ir3_instruction *nop;
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nop = ir3_instr_create(block, 0, OPC_NOP);
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nop->flags |= IR3_INSTR_SS;
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n->flags &= ~IR3_INSTR_SS;
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}
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/* need to be able to set (ss) on first instruction: */
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if ((shader->instrs_count == 0) && (n->category >= 5))
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ir3_instr_create(block, 0, OPC_NOP);
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shader->instrs[shader->instrs_count++] = n;
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if (is_sfu(n))
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regmask_set(&needs_ss, n->regs[0]);
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if (is_tex(n)) {
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if (is_tex(n))
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regmask_set(&needs_sy, n->regs[0]);
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/* both tex/sfu appear to not always immediately consume
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* their src register(s):
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*/
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if (is_tex(n) || is_sfu(n)) {
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for (i = 1; i < n->regs_count; i++) {
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reg = n->regs[i];
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if (reg_gpr(reg))
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regmask_set(&needs_ss_war, reg);
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}
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}
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if (is_input(n))
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last_input = n;
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}
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@ -77,7 +77,7 @@ static unsigned distance(struct ir3_sched_ctx *ctx,
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struct ir3_instruction *n = ctx->scheduled;
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unsigned d = 0;
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while (n && (n != instr) && (d < maxd)) {
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if (!is_meta(n))
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if (is_alu(n) || is_flow(n))
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d++;
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n = n->next;
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}
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