i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcode
This opcode generates code to copy the specified destination index into subregister 5 of the MRF message header. Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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@ -1055,6 +1055,15 @@ enum opcode {
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* - src1 is the destination register when write commit occurs.
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*/
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GS_OPCODE_SVB_WRITE,
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/**
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* Set destination index in the SVB write message payload (M0.5). Used
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* in gen6 for transform feedback.
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*
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* - dst is the header to save the destination indices for SVB WRITE.
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* - src is the register that holds the destination indices value.
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*/
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GS_OPCODE_SVB_SET_DST_INDEX,
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};
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enum brw_derivative_quality {
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@ -530,6 +530,8 @@ brw_instruction_name(enum opcode op)
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return "set_primitive_id";
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case GS_OPCODE_SVB_WRITE:
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return "gs_svb_write";
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case GS_OPCODE_SVB_SET_DST_INDEX:
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return "gs_svb_set_dst_index";
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default:
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/* Yes, this leaks. It's in debug code, it should never occur, and if
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@ -222,6 +222,7 @@ public:
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unsigned sol_binding; /**< gen6: SOL binding table index */
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bool sol_final_write; /**< gen6: send commit message */
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unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
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bool is_send_from_grf();
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bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
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@ -661,6 +662,9 @@ private:
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1);
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void generate_gs_svb_set_destination_index(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src);
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void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
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void generate_gs_prepare_channel_masks(struct brw_reg dst);
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void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
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@ -611,6 +611,20 @@ vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
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brw_pop_insn_state(p);
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}
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void
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vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src)
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{
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int vertex = inst->sol_vertex;
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brw_push_insn_state(p);
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brw_set_default_access_mode(p, BRW_ALIGN_1);
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brw_set_default_mask_control(p, BRW_MASK_DISABLE);
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brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
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brw_pop_insn_state(p);
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}
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void
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vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
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{
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@ -1389,6 +1403,10 @@ vec4_generator::generate_code(const cfg_t *cfg)
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generate_gs_svb_write(inst, dst, src[0], src[1]);
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break;
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case GS_OPCODE_SVB_SET_DST_INDEX:
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generate_gs_svb_set_destination_index(inst, dst, src[0]);
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break;
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case GS_OPCODE_THREAD_END:
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generate_gs_thread_end(inst);
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break;
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