gallivm/nir: Add a short circuit uniform-offset mode for load_ssbo/load_shared.
dEQP-VK.binding_model.buffer_device_address.set3.depth3.basessbo.convertuvec2.nostore.multi.scalar.vert runtime -24.4002% +/- 1.94375% (n=7). The win (I think) is in LLVM not having to chew through handling the extra loops on every constant-offset SSBO load, not in actual rendering time. Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14999>
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@ -1397,8 +1397,9 @@ static void visit_load_ssbo(struct lp_build_nir_context *bld_base,
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{
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LLVMValueRef idx = cast_type(bld_base, get_src(bld_base, instr->src[0]), nir_type_uint, 32);
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LLVMValueRef offset = get_src(bld_base, instr->src[1]);
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bool index_and_offset_are_uniform = nir_src_is_always_uniform(instr->src[0]) && nir_src_is_always_uniform(instr->src[1]);
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bld_base->load_mem(bld_base, nir_dest_num_components(instr->dest), nir_dest_bit_size(instr->dest),
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idx, offset, result);
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index_and_offset_are_uniform, idx, offset, result);
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}
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static void visit_store_ssbo(struct lp_build_nir_context *bld_base,
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@ -1634,8 +1635,9 @@ static void visit_shared_load(struct lp_build_nir_context *bld_base,
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LLVMValueRef result[NIR_MAX_VEC_COMPONENTS])
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{
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LLVMValueRef offset = get_src(bld_base, instr->src[0]);
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bool offset_is_uniform = nir_src_is_always_uniform(instr->src[0]);
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bld_base->load_mem(bld_base, nir_dest_num_components(instr->dest), nir_dest_bit_size(instr->dest),
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NULL, offset, result);
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offset_is_uniform, NULL, offset, result);
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}
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static void visit_shared_store(struct lp_build_nir_context *bld_base,
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@ -111,6 +111,7 @@ struct lp_build_nir_context
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/* for SSBO and shared memory */
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void (*load_mem)(struct lp_build_nir_context *bld_base,
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unsigned nc, unsigned bit_size,
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bool index_and_offset_are_uniform,
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LLVMValueRef index, LLVMValueRef offset, LLVMValueRef result[NIR_MAX_VEC_COMPONENTS]);
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void (*store_mem)(struct lp_build_nir_context *bld_base,
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unsigned writemask, unsigned nc, unsigned bit_size,
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@ -1143,6 +1143,7 @@ mem_access_base_pointer(struct lp_build_nir_context *bld_base,
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static void emit_load_mem(struct lp_build_nir_context *bld_base,
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unsigned nc,
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unsigned bit_size,
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bool index_and_offset_are_uniform,
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LLVMValueRef index,
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LLVMValueRef offset,
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LLVMValueRef outval[NIR_MAX_VEC_COMPONENTS])
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@ -1158,6 +1159,42 @@ static void emit_load_mem(struct lp_build_nir_context *bld_base,
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offset = LLVMBuildAShr(gallivm->builder, offset, lp_build_const_int_vec(gallivm, uint_bld->type, shift_val), "");
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/* If the address is uniform, then use the address from invocation 0 to load,
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* and broadcast to all invocations.
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*/
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if (index_and_offset_are_uniform && invocation_0_must_be_active(bld_base)) {
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LLVMValueRef ssbo_limit;
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LLVMValueRef mem_ptr = mem_access_base_pointer(bld_base, load_bld, bit_size, index,
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lp_build_const_int32(gallivm, 0), &ssbo_limit);
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offset = LLVMBuildExtractElement(gallivm->builder, offset, lp_build_const_int32(gallivm, 0), "");
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for (unsigned c = 0; c < nc; c++) {
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LLVMValueRef chan_offset = LLVMBuildAdd(builder, offset, lp_build_const_int32(gallivm, c), "");
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LLVMValueRef scalar;
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/* If loading outside the SSBO, we need to skip the load and read 0 instead. */
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if (ssbo_limit) {
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LLVMValueRef zero = lp_build_zero_bits(gallivm, bit_size);
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LLVMValueRef res_store = lp_build_alloca(gallivm, LLVMTypeOf(zero), "");
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LLVMBuildStore(builder, zero, res_store);
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LLVMValueRef fetch_cond = LLVMBuildICmp(gallivm->builder, LLVMIntUGE, ssbo_limit, chan_offset, "");
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struct lp_build_if_state ifthen;
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lp_build_if(&ifthen, gallivm, fetch_cond);
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LLVMBuildStore(builder, lp_build_pointer_get(builder, mem_ptr, chan_offset), res_store);
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lp_build_endif(&ifthen);
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scalar = LLVMBuildLoad(builder, res_store, "");
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} else {
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scalar = lp_build_pointer_get(builder, mem_ptr, chan_offset);
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}
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outval[c] = lp_build_broadcast_scalar(load_bld, scalar);
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}
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return;
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}
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/* although the index is dynamically uniform that doesn't count if exec mask isn't set, so read the one-by-one */
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LLVMValueRef result[NIR_MAX_VEC_COMPONENTS];
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