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ac/surface: increment surf_index only when tile swizzle is allowed 

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-07-28 23:08:10 +02:00
parent 9059400247
commit 59144d4bf5
4 changed files with 7 additions and 4 deletions
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6
src/amd/common/ac_surface.c
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@ -30,6 +30,7 @@
#include "amdgpu_id.h" #include "amdgpu_id.h"
#include "ac_gpu_info.h" #include "ac_gpu_info.h"
#include "util/macros.h" #include "util/macros.h"
#include "util/u_atomic.h"
#include "util/u_math.h" #include "util/u_math.h"
#include <errno.h> #include <errno.h>
@ -706,13 +707,14 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED; surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Work out tile swizzle. */ /* Work out tile swizzle. */
if (surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D && if (config->info.surf_index &&
surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
!(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) && !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
(config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) { (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0}; ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0}; ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
AddrBaseSwizzleIn.surfIndex = config->info.surf_index; AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex; AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex; AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo; AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;

2
src/amd/common/ac_surface.h
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@ -209,10 +209,10 @@ struct ac_surf_info {
uint32_t width; uint32_t width;
uint32_t height; uint32_t height;
uint32_t depth; uint32_t depth;
uint32_t surf_index;
uint8_t samples; uint8_t samples;
uint8_t levels; uint8_t levels;
uint16_t array_size; uint16_t array_size;
uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
}; };
struct ac_surf_config { struct ac_surf_config {

2
src/amd/vulkan/radv_image.c
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@ -809,7 +809,7 @@ radv_image_create(VkDevice _device,
image->shareable = vk_find_struct_const(pCreateInfo->pNext, image->shareable = vk_find_struct_const(pCreateInfo->pNext,
EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL; EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) { if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1; image->info.surf_index = &device->image_mrt_offset_counter;
} }
radv_init_surface(device, &image->surface, create_info); radv_init_surface(device, &image->surface, create_info);

1
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
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@ -92,6 +92,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
config.info.levels = tex->last_level + 1; config.info.levels = tex->last_level + 1;
config.is_3d = !!(tex->target == PIPE_TEXTURE_3D); config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE); config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
config.info.surf_index = NULL;
return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf); return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
} }