radv/meta: add srgb conversion to end of resolve shader.
If we are resolving into an srgb dest, we need to convert to linear so the store does the conversion back. This should fix some wierdness seen when we subresolves hit the compute path. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -32,7 +32,7 @@
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#include "vk_format.h"
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static nir_shader *
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build_resolve_compute_shader(struct radv_device *dev, bool is_integer, int samples)
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build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
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{
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nir_builder b;
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char name[64];
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@ -45,7 +45,7 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, int sampl
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false,
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false,
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GLSL_TYPE_FLOAT);
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snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : "float");
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snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
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b.shader->info->name = ralloc_strdup(b.shader, name);
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b.shader->info->cs.local_size[0] = 16;
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@ -158,6 +158,44 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, int sampl
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b.cursor = nir_after_cf_node(&outer_if->cf_node);
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nir_ssa_def *newv = nir_load_var(&b, color);
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if (is_srgb) {
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nir_const_value v;
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unsigned i;
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v.u32[0] = 0x3b4d2e1c; // 0.00313080009
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nir_ssa_def *cmp[3];
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for (i = 0; i < 3; i++)
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cmp[i] = nir_flt(&b, nir_channel(&b, newv, i),
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nir_build_imm(&b, 1, 32, v));
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nir_ssa_def *ltvals[3];
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v.f32[0] = 12.92;
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for (i = 0; i < 3; i++)
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ltvals[i] = nir_fmul(&b, nir_channel(&b, newv, i),
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nir_build_imm(&b, 1, 32, v));
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nir_ssa_def *gtvals[3];
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for (i = 0; i < 3; i++) {
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v.f32[0] = 1.0/2.4;
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gtvals[i] = nir_fpow(&b, nir_channel(&b, newv, i),
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nir_build_imm(&b, 1, 32, v));
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v.f32[0] = 1.055;
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gtvals[i] = nir_fmul(&b, gtvals[i],
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nir_build_imm(&b, 1, 32, v));
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v.f32[0] = 0.055;
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gtvals[i] = nir_fsub(&b, gtvals[i],
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nir_build_imm(&b, 1, 32, v));
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}
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nir_ssa_def *comp[4];
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for (i = 0; i < 3; i++)
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comp[i] = nir_bcsel(&b, cmp[i], ltvals[i], gtvals[i]);
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comp[3] = nir_channels(&b, newv, 3);
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newv = nir_vec(&b, comp, 4);
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}
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nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
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store->src[0] = nir_src_for_ssa(coord);
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@ -230,12 +268,13 @@ static VkResult
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create_resolve_pipeline(struct radv_device *device,
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int samples,
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bool is_integer,
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bool is_srgb,
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VkPipeline *pipeline)
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{
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VkResult result;
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struct radv_shader_module cs = { .nir = NULL };
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cs.nir = build_resolve_compute_shader(device, is_integer, samples);
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cs.nir = build_resolve_compute_shader(device, is_integer, is_srgb, samples);
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/* compute shader */
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@ -282,12 +321,15 @@ radv_device_init_meta_resolve_compute_state(struct radv_device *device)
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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uint32_t samples = 1 << i;
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res = create_resolve_pipeline(device, samples, false,
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res = create_resolve_pipeline(device, samples, false, false,
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&state->resolve_compute.rc[i].pipeline);
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res = create_resolve_pipeline(device, samples, true,
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res = create_resolve_pipeline(device, samples, true, false,
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&state->resolve_compute.rc[i].i_pipeline);
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res = create_resolve_pipeline(device, samples, false, true,
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&state->resolve_compute.rc[i].srgb_pipeline);
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}
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return res;
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@ -305,6 +347,10 @@ radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->resolve_compute.rc[i].i_pipeline,
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&state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->resolve_compute.rc[i].srgb_pipeline,
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&state->alloc);
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}
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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@ -443,6 +489,8 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
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VkPipeline pipeline;
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if (vk_format_is_int(src_image->vk_format))
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].i_pipeline;
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else if (vk_format_is_srgb(src_image->vk_format))
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
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else
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].pipeline;
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if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) {
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@ -415,6 +415,7 @@ struct radv_meta_state {
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struct {
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VkPipeline pipeline;
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VkPipeline i_pipeline;
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VkPipeline srgb_pipeline;
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} rc[MAX_SAMPLES_LOG2];
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} resolve_compute;
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@ -396,6 +396,13 @@ vk_format_is_int(VkFormat format)
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return channel >= 0 && desc->channel[channel].pure_integer;
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}
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static inline bool
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vk_format_is_srgb(VkFormat format)
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{
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const struct vk_format_description *desc = vk_format_description(format);
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return desc->colorspace == VK_FORMAT_COLORSPACE_SRGB;
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}
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static inline VkFormat
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vk_format_stencil_only(VkFormat format)
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{
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