i965/skl: Don't use ALL_SLICES_AT_EACH_LOD

The render surface state command for Skylake doesn't have the surface
array spacing bit so it's not possible to select this layout. I think
it was only used in order to make it pick a tightly-packed qpitch
value that doesn't include space for the mipmaps. However this won't
be necessary after the next patch because it will automatically pick a
packed qpitch value whenever first_level==last_level. It is better to
remove this layout entirely on Gen8+ because although it can
effectively be implemented with a small qpitch value when there are no
mipmaps it isn't possible to support the case where there are mipmaps
because in that case the layout is very different.

It could be good to make a similar change for Gen8 if we also change
the layouting code to pick the qpitch value in a similar way.

v2: Make the commit message and comments more convincing

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Neil Roberts 2015-02-20 19:11:46 +00:00
parent c1485f4b7d
commit 584f8e1ec5
1 changed files with 20 additions and 10 deletions

View File

@ -388,19 +388,29 @@ intel_miptree_create_layout(struct brw_context *brw,
}
}
/* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
* can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
/* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
* be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
* Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
* used on Gen8 to make it pick a qpitch value which doesn't include space
* for the mipmaps. On Gen9 this is not necessary because it will
* automatically pick a packed qpitch value whenever mt->first_level ==
* mt->last_level.
* TODO: can we use it elsewhere?
* TODO: also disable this on Gen8 and pick the qpitch value like Gen9
*/
switch (mt->msaa_layout) {
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
if (brw->gen >= 9) {
mt->array_layout = ALL_LOD_IN_EACH_SLICE;
break;
case INTEL_MSAA_LAYOUT_UMS:
case INTEL_MSAA_LAYOUT_CMS:
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
break;
} else {
switch (mt->msaa_layout) {
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
mt->array_layout = ALL_LOD_IN_EACH_SLICE;
break;
case INTEL_MSAA_LAYOUT_UMS:
case INTEL_MSAA_LAYOUT_CMS:
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
break;
}
}
if (target == GL_TEXTURE_CUBE_MAP) {