iris: some shader bits
This commit is contained in:
Kenneth Graunke
parent
df401aaa11
commit
581459a9fe
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@ -72,6 +72,7 @@ enum iris_dirty {
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IRIS_DIRTY_FS = (1ull << 32),
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IRIS_DIRTY_CS = (1ull << 33),
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IRIS_DIRTY_STATE_BASE_ADDRESS = (1ull << 34),
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IRIS_DIRTY_URB = (1ull << 35),
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};
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struct iris_depth_stencil_alpha_state;
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@ -108,6 +108,9 @@ iris_bind_tes_state(struct pipe_context *ctx, void *hwcso)
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{
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struct iris_context *ice = (struct iris_context *)ctx;
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if (!!hwcso != !!ice->shaders.progs[MESA_SHADER_TESS_EVAL])
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ice->state.dirty |= IRIS_DIRTY_URB;
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ice->shaders.progs[MESA_SHADER_TESS_EVAL] = hwcso;
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ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TES;
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}
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@ -117,6 +120,9 @@ iris_bind_gs_state(struct pipe_context *ctx, void *hwcso)
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{
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struct iris_context *ice = (struct iris_context *)ctx;
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if (!!hwcso != !!ice->shaders.progs[MESA_SHADER_GEOMETRY])
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ice->state.dirty |= IRIS_DIRTY_URB;
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ice->shaders.progs[MESA_SHADER_GEOMETRY] = hwcso;
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ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_GS;
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}
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@ -261,6 +267,24 @@ iris_update_compiled_vs(struct iris_context *ice)
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iris_compile_vs(ice, ice->shaders.progs[MESA_SHADER_VERTEX], &key);
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}
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static void
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iris_update_compiled_tcs(struct iris_context *ice)
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{
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// XXX: TCS
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}
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static void
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iris_update_compiled_tes(struct iris_context *ice)
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{
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// XXX: TES
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}
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static void
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iris_update_compiled_gs(struct iris_context *ice)
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{
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// XXX: GS
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}
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static bool
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iris_compile_fs(struct iris_context *ice,
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struct iris_uncompiled_shader *ish,
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@ -379,10 +403,35 @@ update_last_vue_map(struct iris_context *ice)
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void
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iris_update_compiled_shaders(struct iris_context *ice)
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{
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struct brw_vue_prog_data *old_prog_datas[4];
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if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++)
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old_prog_datas[i] = (void *) ice->shaders.prog_data[i];
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}
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iris_update_compiled_vs(ice);
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iris_update_compiled_tcs(ice);
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iris_update_compiled_tes(ice);
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iris_update_compiled_gs(ice);
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update_last_vue_map(ice);
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iris_update_compiled_fs(ice);
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// ...
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if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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struct brw_vue_prog_data *old = old_prog_datas[i];
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struct brw_vue_prog_data *new = (void *) ice->shaders.prog_data[i];
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if (!!old != !!new ||
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(new && new->urb_entry_size != old->urb_entry_size)) {
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ice->state.dirty |= IRIS_DIRTY_URB;
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break;
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}
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}
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}
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if (ice->state.dirty & IRIS_DIRTY_URB) {
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// ... back to the state module :/
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}
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}
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void
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@ -1367,6 +1367,9 @@ iris_upload_render_state(struct iris_context *ice,
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{
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const uint64_t dirty = ice->state.dirty;
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if (dirty & IRIS_DIRTY_URB) {
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}
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if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
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struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
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struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
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@ -1624,6 +1627,7 @@ iris_upload_render_state(struct iris_context *ice,
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3DSTATE_GS
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3DSTATE_PS_EXTRA
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3DSTATE_PS
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3DSTATE_STREAMOUT
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3DSTATE_SO_BUFFER
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3DSTATE_SO_DECL_LIST
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@ -1649,6 +1653,212 @@ iris_bind_compute_state(struct pipe_context *ctx, void *state)
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{
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}
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//pkt.SamplerCount = \
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//DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
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//pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
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//ffs(stage_state->per_thread_scratch) - 11; \
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#define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
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pkt.KernelStartPointer = prog_offset; \
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pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
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pkt.FloatingPointMode = prog_data->use_alt_mode; \
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\
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pkt.DispatchGRFStartRegisterForURBData = \
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prog_data->dispatch_grf_start_reg; \
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pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
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pkt.prefix##URBEntryReadOffset = 0; \
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\
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pkt.StatisticsEnable = true; \
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pkt.Enable = true;
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static void
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iris_create_vs_state(struct gen_device_info *devinfo,
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struct brw_vs_prog_data *vs_prog_data,
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unsigned prog_offset)
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{
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struct brw_vue_prog_data *vue_prog_data = &vs_prog_data->base;
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struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
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uint32_t vs_state[GENX(3DSTATE_VS_length)];
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iris_pack_command(GENX(3DSTATE_VS), vs_state, vs) {
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INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
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vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
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vs.SIMD8DispatchEnable = true;
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vs.UserClipDistanceCullTestEnableBitmask =
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vue_prog_data->cull_distance_mask;
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}
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}
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static void
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iris_create_tcs_state(struct gen_device_info *devinfo,
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struct brw_tcs_prog_data *tcs_prog_data,
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unsigned prog_offset)
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{
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struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
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struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
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uint32_t hs_state[GENX(3DSTATE_HS_length)];
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iris_pack_command(GENX(3DSTATE_HS), hs_state, hs) {
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INIT_THREAD_DISPATCH_FIELDS(hs, Vertex);
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hs.InstanceCount = tcs_prog_data->instances - 1;
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hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
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hs.IncludeVertexHandles = true;
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}
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}
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static void
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iris_create_tes_state(struct gen_device_info *devinfo,
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struct brw_tes_prog_data *tes_prog_data,
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unsigned prog_offset)
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{
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struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
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struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
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uint32_t ds_state[GENX(3DSTATE_DS_length)];
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iris_pack_command(GENX(3DSTATE_DS), ds_state, ds) {
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INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
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ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
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ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
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ds.ComputeWCoordinateEnable =
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tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
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ds.UserClipDistanceCullTestEnableBitmask =
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vue_prog_data->cull_distance_mask;
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}
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}
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static void
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iris_create_gs_state(struct gen_device_info *devinfo,
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struct brw_gs_prog_data *gs_prog_data,
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unsigned prog_offset)
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{
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struct brw_vue_prog_data *vue_prog_data = &gs_prog_data->base;
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struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
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uint32_t gs_state[GENX(3DSTATE_GS_length)];
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iris_pack_command(GENX(3DSTATE_GS), gs_state, gs) {
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INIT_THREAD_DISPATCH_FIELDS(gs, Vertex);
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gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
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gs.OutputTopology = gs_prog_data->output_topology;
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gs.ControlDataHeaderSize =
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gs_prog_data->control_data_header_size_hwords;
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gs.InstanceControl = gs_prog_data->invocations - 1;
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gs.DispatchMode = SIMD8;
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gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
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gs.ControlDataFormat = gs_prog_data->control_data_format;
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gs.ReorderMode = TRAILING;
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gs.ExpectedVertexCount = gs_prog_data->vertices_in;
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gs.MaximumNumberofThreads =
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GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1)
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: (devinfo->max_gs_threads - 1);
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if (gs_prog_data->static_vertex_count != -1) {
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gs.StaticOutput = true;
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gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count;
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}
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gs.IncludeVertexHandles = vue_prog_data->include_vue_handles;
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gs.UserClipDistanceCullTestEnableBitmask =
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vue_prog_data->cull_distance_mask;
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const int urb_entry_write_offset = 1;
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const uint32_t urb_entry_output_length =
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DIV_ROUND_UP(vue_prog_data->vue_map.num_slots, 2) -
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urb_entry_write_offset;
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gs.VertexURBEntryOutputReadOffset = urb_entry_write_offset;
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gs.VertexURBEntryOutputLength = MAX2(urb_entry_output_length, 1);
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}
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}
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static void
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iris_create_fs_state(struct gen_device_info *devinfo,
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struct brw_wm_prog_data *wm_prog_data,
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unsigned prog_offset)
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{
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struct brw_stage_prog_data *prog_data = &wm_prog_data->base;
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uint32_t ps_state[GENX(3DSTATE_PS_length)];
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uint32_t psx_state[GENX(3DSTATE_PS_EXTRA_length)];
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iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) {
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ps.VectorMaskEnable = true;
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//ps.SamplerCount = ...
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ps.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4;
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ps.FloatingPointMode = prog_data->use_alt_mode;
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ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1);
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ps.PushConstantEnable = prog_data->nr_params > 0 ||
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prog_data->ubo_ranges[0].length > 0;
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/* From the documentation for this packet:
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* "If the PS kernel does not need the Position XY Offsets to
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* compute a Position Value, then this field should be programmed
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* to POSOFFSET_NONE."
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*
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* "SW Recommendation: If the PS kernel needs the Position Offsets
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* to compute a Position XY value, this field should match Position
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* ZW Interpolation Mode to ensure a consistent position.xyzw
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* computation."
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*
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* We only require XY sample offsets. So, this recommendation doesn't
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* look useful at the moment. We might need this in future.
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*/
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ps.PositionXYOffsetSelect =
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wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
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ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
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ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
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ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
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// XXX: Disable SIMD32 with 16x MSAA
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
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ps.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
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ps.KernelStartPointer0 =
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prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
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ps.KernelStartPointer1 =
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prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
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ps.KernelStartPointer2 =
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prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
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}
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iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) {
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psx.PixelShaderValid = true;
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psx.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
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psx.PixelShaderKillsPixel = wm_prog_data->uses_kill;
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psx.AttributeEnable = wm_prog_data->num_varying_inputs != 0;
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psx.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
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psx.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
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psx.PixelShaderIsPerSample = wm_prog_data->persample_dispatch;
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if (wm_prog_data->uses_sample_mask) {
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/* TODO: conservative rasterization */
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if (wm_prog_data->post_depth_coverage)
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psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
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else
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psx.InputCoverageMaskState = ICMS_NORMAL;
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}
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psx.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
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psx.PixelShaderPullsBary = wm_prog_data->pulls_bary;
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psx.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
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// XXX: UAV bit
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}
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}
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void
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iris_destroy_state(struct iris_context *ice)
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{
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