radeonsi: write shader descriptors into hang reports
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
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6caa558ca6
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57b9d75af5
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@ -674,6 +674,112 @@ static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
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}
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}
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}
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}
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static void si_dump_descriptor_list(struct si_descriptors *desc,
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const char *shader_name,
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const char *elem_name,
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unsigned num_elements,
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FILE *f)
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{
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unsigned i, j;
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uint32_t *cpu_list = desc->list;
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uint32_t *gpu_list = desc->gpu_list;
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const char *list_note = "GPU list";
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if (!gpu_list) {
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gpu_list = cpu_list;
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list_note = "CPU list";
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}
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for (i = 0; i < num_elements; i++) {
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fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n",
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shader_name, elem_name, i, list_note);
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switch (desc->element_dw_size) {
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case 4:
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for (j = 0; j < 4; j++)
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si_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
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gpu_list[j], 0xffffffff);
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break;
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case 8:
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for (j = 0; j < 8; j++)
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si_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
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gpu_list[j], 0xffffffff);
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fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
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for (j = 0; j < 4; j++)
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si_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
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gpu_list[4+j], 0xffffffff);
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break;
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case 16:
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for (j = 0; j < 8; j++)
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si_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
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gpu_list[j], 0xffffffff);
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fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
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for (j = 0; j < 4; j++)
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si_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
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gpu_list[4+j], 0xffffffff);
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fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
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for (j = 0; j < 8; j++)
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si_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
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gpu_list[8+j], 0xffffffff);
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fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n");
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for (j = 0; j < 4; j++)
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si_dump_reg(f, R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
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gpu_list[12+j], 0xffffffff);
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break;
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}
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if (memcmp(gpu_list, cpu_list, desc->element_dw_size * 4) != 0) {
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fprintf(f, COLOR_RED "!!!!! This slot was corrupted in GPU memory !!!!!"
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COLOR_RESET "\n");
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}
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fprintf(f, "\n");
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gpu_list += desc->element_dw_size;
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cpu_list += desc->element_dw_size;
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}
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}
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static void si_dump_descriptors(struct si_context *sctx,
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struct si_shader_ctx_state *state,
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FILE *f)
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{
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if (!state->cso || !state->current)
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return;
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unsigned type = state->cso->type;
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const struct tgsi_shader_info *info = &state->cso->info;
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struct si_descriptors *descs =
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&sctx->descriptors[SI_DESCS_FIRST_SHADER +
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type * SI_NUM_SHADER_DESCS];
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static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
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static const char *elem_name[] = {
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" - Constant buffer",
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" - Shader buffer",
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" - Sampler",
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" - Image",
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};
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unsigned num_elements[] = {
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util_last_bit(info->const_buffers_declared),
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util_last_bit(info->shader_buffers_declared),
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util_last_bit(info->samplers_declared),
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util_last_bit(info->images_declared),
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};
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if (type == PIPE_SHADER_VERTEX) {
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si_dump_descriptor_list(&sctx->vertex_buffers, shader_name[type],
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" - Vertex buffer", info->num_inputs, f);
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}
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for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
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si_dump_descriptor_list(descs, shader_name[type], elem_name[i],
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num_elements[i], f);
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}
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static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
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static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
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unsigned flags)
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unsigned flags)
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{
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{
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@ -691,6 +797,14 @@ static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
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si_dump_shader(sctx->screen, &sctx->tes_shader, f);
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si_dump_shader(sctx->screen, &sctx->tes_shader, f);
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si_dump_shader(sctx->screen, &sctx->gs_shader, f);
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si_dump_shader(sctx->screen, &sctx->gs_shader, f);
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si_dump_shader(sctx->screen, &sctx->ps_shader, f);
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si_dump_shader(sctx->screen, &sctx->ps_shader, f);
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si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
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"", "RW buffers", SI_NUM_RW_BUFFERS, f);
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si_dump_descriptors(sctx, &sctx->vs_shader, f);
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si_dump_descriptors(sctx, &sctx->tcs_shader, f);
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si_dump_descriptors(sctx, &sctx->tes_shader, f);
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si_dump_descriptors(sctx, &sctx->gs_shader, f);
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si_dump_descriptors(sctx, &sctx->ps_shader, f);
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}
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}
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if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
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if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
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@ -241,6 +241,7 @@ static bool si_upload_descriptors(struct si_context *sctx,
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return false; /* skip the draw call */
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return false; /* skip the draw call */
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util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
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util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
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desc->gpu_list = ptr;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
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RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
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RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
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@ -217,6 +217,8 @@ enum {
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struct si_descriptors {
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struct si_descriptors {
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/* The list of descriptors in malloc'd memory. */
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/* The list of descriptors in malloc'd memory. */
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uint32_t *list;
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uint32_t *list;
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/* The list in mapped GPU memory. */
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uint32_t *gpu_list;
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/* The size of one descriptor. */
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/* The size of one descriptor. */
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unsigned element_dw_size;
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unsigned element_dw_size;
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/* The maximum number of descriptors. */
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/* The maximum number of descriptors. */
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