freedreno/a3xx/compiler: handle kill properly (new compiler)
Since 'kill' does not produce a result, the new compiler was happily optimizing them out. We need to instead track 'kill's similar to outputs. But since there is no non-predicated kill instruction, (and for flattend if/else we do want them to be predicated), we need to track the topmost branch condition on the stack and use that as src arg to the kill. For a kill at the topmost level, we have to generate an immediate 1.0 to feed into the cmps.f for setting the predicate register. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
e35747b882
commit
579473f8f8
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@ -103,9 +103,16 @@ struct fd3_compile_context {
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/* stack of branch instructions that mark (potentially nested)
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* branch if/else/loop/etc
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*/
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struct ir3_instruction *branch[16];
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struct {
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struct ir3_instruction *instr, *cond;
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bool inv; /* true iff in else leg of branch */
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} branch[16];
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unsigned int branch_count;
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/* list of kill instructions: */
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struct ir3_instruction *kill[16];
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unsigned int kill_count;
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/* used when dst is same as one of the src, to avoid overwriting a
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* src element before the remaining scalar instructions that make
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* up the vector operation
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@ -135,6 +142,7 @@ compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
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ctx->next_inloc = 8;
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ctx->num_internal_temps = 0;
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ctx->branch_count = 0;
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ctx->kill_count = 0;
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ctx->block = NULL;
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ctx->current_instr = NULL;
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ctx->num_output_updates = 0;
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@ -274,6 +282,9 @@ push_block(struct fd3_compile_context *ctx)
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ntmp = SCALAR_REGS(TEMPORARY);
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ntmp += 4 * 4;
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nout = SCALAR_REGS(OUTPUT);
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nin = SCALAR_REGS(INPUT);
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/* for outermost block, 'inputs' are the actual shader INPUT
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* register file. Reads from INPUT registers always go back to
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* top block. For nested blocks, 'inputs' is used to track any
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@ -284,17 +295,19 @@ push_block(struct fd3_compile_context *ctx)
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/* NOTE: fragment shaders actually have two inputs (r0.xy, the
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* position)
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*/
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nin = SCALAR_REGS(INPUT);
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if (ctx->type == TGSI_PROCESSOR_FRAGMENT)
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if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
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nin = MAX2(2, nin);
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nout += ARRAY_SIZE(ctx->kill);
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}
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} else {
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nin = ntmp;
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}
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nout = SCALAR_REGS(OUTPUT);
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block = ir3_block_create(ctx->ir, ntmp, nin, nout);
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if ((ctx->type == TGSI_PROCESSOR_FRAGMENT) && !ctx->block)
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block->noutputs -= ARRAY_SIZE(ctx->kill);
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block->parent = ctx->block;
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ctx->block = block;
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@ -1246,15 +1259,23 @@ trans_cmp(const struct instr_translater *t,
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*/
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static void
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push_branch(struct fd3_compile_context *ctx, struct ir3_instruction *instr)
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push_branch(struct fd3_compile_context *ctx, bool inv,
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struct ir3_instruction *instr, struct ir3_instruction *cond)
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{
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ctx->branch[ctx->branch_count++] = instr;
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unsigned int idx = ctx->branch_count++;
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compile_assert(ctx, idx < ARRAY_SIZE(ctx->branch));
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ctx->branch[idx].instr = instr;
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ctx->branch[idx].inv = inv;
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/* else side of branch has same condition: */
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if (!inv)
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ctx->branch[idx].cond = cond;
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}
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static struct ir3_instruction *
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pop_branch(struct fd3_compile_context *ctx)
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{
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return ctx->branch[--ctx->branch_count];
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unsigned int idx = --ctx->branch_count;
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return ctx->branch[idx].instr;
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}
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static void
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@ -1262,7 +1283,7 @@ trans_if(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct ir3_instruction *instr, *cond;
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struct tgsi_src_register *src = &inst->Src[0].Register;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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@ -1274,25 +1295,22 @@ trans_if(const struct instr_translater *t,
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if (is_const(src))
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src = get_unconst(ctx, src);
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/* cmps.f.eq tmp0, b, {0.0} */
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/* cmps.f.ne tmp0, b, {0.0} */
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instr = instr_create(ctx, 2, OPC_CMPS_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src, src->SwizzleX);
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add_src_reg(ctx, instr, &constval, constval.SwizzleX);
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instr->cat2.condition = IR3_COND_EQ;
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instr->cat2.condition = IR3_COND_NE;
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/* add.s tmp0, tmp0, -1 */
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instr = instr_create(ctx, 2, OPC_ADD_S);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
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compile_assert(ctx, instr->regs[1]->flags & IR3_REG_SSA); /* because get_unconst() */
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cond = instr->regs[1]->instr;
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/* meta:flow tmp0 */
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instr = instr_create(ctx, -1, OPC_META_FLOW);
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ir3_reg_create(instr, 0, 0); /* dummy dst */
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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push_branch(ctx, instr);
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push_branch(ctx, false, instr, cond);
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instr->flow.if_block = push_block(ctx);
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}
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@ -1310,7 +1328,7 @@ trans_else(const struct instr_translater *t,
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compile_assert(ctx, (instr->category == -1) &&
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(instr->opc == OPC_META_FLOW));
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push_branch(ctx, instr);
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push_branch(ctx, true, instr, NULL);
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instr->flow.else_block = push_block(ctx);
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}
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@ -1483,6 +1501,53 @@ trans_endif(const struct instr_translater *t,
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// TODO maybe we want to compact block->inputs?
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}
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/*
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* Kill / Kill-if
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*/
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static void
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trans_kill(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr, *immed, *cond = NULL;
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bool inv = false;
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switch (t->tgsi_opc) {
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case TGSI_OPCODE_KILL:
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/* unconditional kill, use enclosing if condition: */
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if (ctx->branch_count > 0) {
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unsigned int idx = ctx->branch_count - 1;
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cond = ctx->branch[idx].cond;
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inv = ctx->branch[idx].inv;
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} else {
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cond = create_immed(ctx, 1.0);
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}
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break;
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}
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compile_assert(ctx, cond);
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immed = create_immed(ctx, 0.0);
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/* cmps.f.ne p0.x, cond, {0.0} */
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instr = instr_create(ctx, 2, OPC_CMPS_F);
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instr->cat2.condition = IR3_COND_NE;
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ir3_reg_create(instr, regid(REG_P0, 0), 0);
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ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = cond;
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ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = immed;
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cond = instr;
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/* kill p0.x */
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instr = instr_create(ctx, 0, OPC_KILL);
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instr->cat0.inv = inv;
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ir3_reg_create(instr, 0, 0); /* dummy dst */
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ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = cond;
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ctx->kill[ctx->kill_count++] = instr;
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}
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/*
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* Handlers for TGSI instructions which do have 1:1 mapping to native
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* instructions:
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@ -1672,7 +1737,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
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INSTR(ELSE, trans_else),
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INSTR(ENDIF, trans_endif),
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INSTR(END, instr_cat0, .opc = OPC_END),
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INSTR(KILL, instr_cat0, .opc = OPC_KILL),
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INSTR(KILL, trans_kill, .opc = OPC_KILL),
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};
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static fd3_semantic
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@ -1944,6 +2009,16 @@ fd3_compile_shader(struct fd3_shader_stateobj *so,
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compile_instructions(&ctx);
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/* at this point, we want the kill's in the outputs array too,
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* so that they get scheduled (since they have no dst).. we've
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* already ensured that the array is big enough in push_block():
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*/
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if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
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struct ir3_block *block = ctx.block;
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for (i = 0; i < ctx.kill_count; i++)
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block->outputs[block->noutputs++] = ctx.kill[i];
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}
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if (fd_mesa_debug & FD_DBG_OPTDUMP)
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compile_dump(&ctx);
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@ -307,6 +307,11 @@ static inline uint32_t reg_comp(struct ir3_register *reg)
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return reg->num & 0x3;
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}
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static inline bool is_flow(struct ir3_instruction *instr)
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{
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return (instr->category == 0);
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}
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static inline bool is_alu(struct ir3_instruction *instr)
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{
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return (1 <= instr->category) && (instr->category <= 3);
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@ -336,11 +341,6 @@ static inline bool is_meta(struct ir3_instruction *instr)
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return (instr->category == -1);
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}
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static inline bool is_gpr(struct ir3_register *reg)
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{
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return !(reg->flags & (IR3_REG_CONST | IR3_REG_IMMED));
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}
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/* TODO combine is_gpr()/reg_gpr().. */
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static inline bool reg_gpr(struct ir3_register *r)
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{
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@ -68,7 +68,7 @@ int ir3_delayslots(struct ir3_instruction *assigner,
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return 0;
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/* assigner must be alu: */
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if (is_sfu(consumer) || is_tex(consumer)) {
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if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer)) {
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return 8;
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} else if ((consumer->category == 3) &&
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is_mad(consumer->opc) && (n == 2)) {
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@ -456,6 +456,10 @@ static void ir3_instr_ra(struct ir3_ra_ctx *ctx,
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if (instr->regs_count == 0)
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return;
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/* skip writes to a0, p0, etc */
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if (!reg_gpr(instr->regs[0]))
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return;
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/* if we've already visited this instruction, bail now: */
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if (instr->flags & IR3_INSTR_MARK)
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return;
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@ -493,7 +497,7 @@ static void legalize(struct ir3_ra_ctx *ctx, struct ir3_block *block)
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for (i = 1; i < n->regs_count; i++) {
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struct ir3_register *reg = n->regs[i];
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if (is_gpr(reg)) {
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if (reg_gpr(reg)) {
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/* TODO: we probably only need (ss) for alu
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* instr consuming sfu result.. need to make
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