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r600g: only set depth bit for hw accessible depth buffers. 

If we get a sw accessible buffer like the S8 texture we end up
doing depth tracking on it when there is no need since we won't
ever bind it to the hardware. This leads to a sw fallback in the
transfer destruction which leads to and endless recusion loop
of fail in transfer destroy.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2011-02-03 13:19:30 +10:00
parent b13b7b86b2
commit 5730d56549
1 changed files with 46 additions and 46 deletions
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92
src/gallium/drivers/r600/r600_texture.c
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@ -278,52 +278,6 @@ static void r600_setup_miptree(struct pipe_screen *screen,
rtex->size = offset;
}
static struct r600_resource_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned array_mode,
unsigned pitch_in_bytes_override,
unsigned max_buffer_size,
struct r600_bo *bo)
{
struct r600_resource_texture *rtex;
struct r600_resource *resource;
struct radeon *radeon = (struct radeon *)screen->winsys;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (rtex == NULL)
return NULL;
resource = &rtex->resource;
resource->base.b = *base;
resource->base.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->base.b.reference, 1);
resource->base.b.screen = screen;
resource->bo = bo;
rtex->pitch_override = pitch_in_bytes_override;
if (util_format_is_depth_or_stencil(base->format))
rtex->depth = 1;
if (array_mode)
rtex->tiled = 1;
r600_setup_miptree(screen, rtex, array_mode);
resource->size = rtex->size;
if (!resource->bo) {
struct pipe_resource *ptex = &rtex->resource.base.b;
int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
if (!resource->bo) {
FREE(rtex);
return NULL;
}
}
return rtex;
}
/* Figure out whether u_blitter will fallback to a transfer operation.
* If so, don't use a staging resource.
*/
@ -363,6 +317,52 @@ static boolean permit_hardware_blit(struct pipe_screen *screen,
return TRUE;
}
static struct r600_resource_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned array_mode,
unsigned pitch_in_bytes_override,
unsigned max_buffer_size,
struct r600_bo *bo)
{
struct r600_resource_texture *rtex;
struct r600_resource *resource;
struct radeon *radeon = (struct radeon *)screen->winsys;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (rtex == NULL)
return NULL;
resource = &rtex->resource;
resource->base.b = *base;
resource->base.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->base.b.reference, 1);
resource->base.b.screen = screen;
resource->bo = bo;
rtex->pitch_override = pitch_in_bytes_override;
/* only mark depth textures the HW can hit as depth textures */
if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
rtex->depth = 1;
if (array_mode)
rtex->tiled = 1;
r600_setup_miptree(screen, rtex, array_mode);
resource->size = rtex->size;
if (!resource->bo) {
struct pipe_resource *ptex = &rtex->resource.base.b;
int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
if (!resource->bo) {
FREE(rtex);
return NULL;
}
}
return rtex;
}
struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{