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ac/surface: enable DCC for the first level in the mip tail on gfx10 

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>
This commit is contained in:
Marek Olšák 2020-06-11 04:30:04 -04:00 committed by Marge Bot
parent 7406ea37e6
commit 56f2a77a41
1 changed files with 10 additions and 1 deletions
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11
src/amd/common/ac_surface.c
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@ -1481,7 +1481,16 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib,
*/
for (unsigned i = 0; i < in->numMipLevels; i++) {
if (meta_mip_info[i].inMiptail) {
surf->num_dcc_levels = i;
/* GFX10 can only compress the first level
* in the mip tail.
*
* TODO: Try to do the same thing for gfx9
* if there are no regressions.
*/
if (info->chip_class >= GFX10)
surf->num_dcc_levels = i + 1;
else
surf->num_dcc_levels = i;
break;
}
}