cell: Added DPH instruction and verified against softpipe.
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@ -633,6 +633,45 @@ emit_DP4(struct codegen *gen, const struct tgsi_full_instruction *inst)
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return true;
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return true;
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}
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}
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/**
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* Emit homogeneous dot product. See emit_ADD for comments.
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*/
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static boolean
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emit_DPH(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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spe_comment(gen->f, -4, "DPH:");
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int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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int d_reg = get_dst_reg(gen, CHAN_X, &inst->FullDstRegisters[0]);
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/* d = x * x */
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spe_fm(gen->f, d_reg, s1_reg, s2_reg);
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s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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/* d = y * y + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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/* d = z * z + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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s2_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
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/* d = w + d */
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spe_fa(gen->f, d_reg, s2_reg, d_reg);
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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}
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}
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free_itemps(gen);
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return true;
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}
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/**
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/**
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* Emit set-if-greater-than.
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* Emit set-if-greater-than.
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* Note that the SPE fcgt instruction produces 0x0 and 0xffffffff as
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* Note that the SPE fcgt instruction produces 0x0 and 0xffffffff as
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@ -1124,6 +1163,8 @@ emit_instruction(struct codegen *gen,
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return emit_DP3(gen, inst);
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return emit_DP3(gen, inst);
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case TGSI_OPCODE_DP4:
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case TGSI_OPCODE_DP4:
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return emit_DP4(gen, inst);
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return emit_DP4(gen, inst);
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case TGSI_OPCODE_DPH:
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return emit_DPH(gen, inst);
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case TGSI_OPCODE_RCP:
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case TGSI_OPCODE_RCP:
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return emit_RCP(gen, inst);
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return emit_RCP(gen, inst);
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case TGSI_OPCODE_RSQ:
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case TGSI_OPCODE_RSQ:
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