anv/pipeline: Silently pass tests if depth or stencil is missing
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
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@ -155,6 +155,8 @@ genX(graphics_pipeline_create)(
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VkPipeline* pPipeline)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
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struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
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struct anv_pipeline *pipeline;
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VkResult result;
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@ -178,7 +180,7 @@ genX(graphics_pipeline_create)(
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assert(pCreateInfo->pRasterizationState);
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gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
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gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
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pCreateInfo->pMultisampleState);
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@ -268,6 +268,8 @@ genX(graphics_pipeline_create)(
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VkPipeline* pPipeline)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
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struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
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struct anv_pipeline *pipeline;
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VkResult result;
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uint32_t offset, length;
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@ -294,7 +296,7 @@ genX(graphics_pipeline_create)(
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emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
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pCreateInfo->pMultisampleState, extra);
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emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
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emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
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pCreateInfo->pMultisampleState);
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@ -21,6 +21,8 @@
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* IN THE SOFTWARE.
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*/
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#include "vk_format_info.h"
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static uint32_t
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vertex_element_comp_control(enum isl_format format, unsigned comp)
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{
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@ -428,7 +430,9 @@ static const uint32_t vk_to_gen_stencil_op[] = {
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static void
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emit_ds_state(struct anv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *info)
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const VkPipelineDepthStencilStateCreateInfo *info,
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const struct anv_render_pass *pass,
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const struct anv_subpass *subpass)
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{
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#if GEN_GEN == 7
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# define depth_stencil_dw pipeline->gen7.depth_stencil_state
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@ -470,6 +474,30 @@ emit_ds_state(struct anv_pipeline *pipeline,
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.BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
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};
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VkImageAspectFlags aspects = 0;
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if (pass->attachments == NULL) {
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/* This comes from meta. Assume we have verything. */
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aspects = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
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} else if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
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VkFormat depth_stencil_format =
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pass->attachments[subpass->depth_stencil_attachment].format;
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aspects = vk_format_aspects(depth_stencil_format);
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}
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/* The Vulkan spec requires that if either depth or stencil is not present,
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* the pipeline is to act as if the test silently passes.
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*/
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if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
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depth_stencil.DepthBufferWriteEnable = false;
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depth_stencil.DepthTestFunction = PREFILTEROPALWAYS;
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}
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if (!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
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depth_stencil.StencilBufferWriteEnable = false;
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depth_stencil.StencilTestFunction = PREFILTEROPALWAYS;
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depth_stencil.BackfaceStencilTestFunction = PREFILTEROPALWAYS;
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}
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/* From the Broadwell PRM:
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*
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* "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
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