etnaviv: Set SE.CLIP registers, add margins for scissor/clip registers
This fixes rendering of full-screen quads (and other screen-filling geometry, e.g. ioquake3 walls up-close) on gc3000. It should be a no-op on other hardware. - It looks like SE_CLIP registers were not set at all. I'm amazed that rendering worked without them. Emit them to avoid issues on gc3000. - Define constants ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119) ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111) ETNA_SE_CLIP_MARGIN_RIGHT (0xffff) ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff) These demarcate the margin (fixp16) between the computed sizes and the value sent to the chip. I have set these to the numbers used by the Vivante driver for gc2000. I am not sure whether any old hardware was relying on the old numbers, or whether those were just a guess. But if so, these need to be moved to the _specs structure. CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com> Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
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@ -491,6 +491,23 @@ etna_emit_state(struct etna_context *ctx)
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/*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, rasterizer->SE_DEPTH_BIAS);
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/*00C18*/ EMIT_STATE(SE_CONFIG, rasterizer->SE_CONFIG);
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}
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if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
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ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) {
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struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
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uint32_t clip_right =
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MIN2(ctx->framebuffer.SE_CLIP_RIGHT, ctx->viewport.SE_CLIP_RIGHT);
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uint32_t clip_bottom =
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MIN2(ctx->framebuffer.SE_CLIP_BOTTOM, ctx->viewport.SE_CLIP_BOTTOM);
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if (rasterizer->scissor) {
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clip_right = MIN2(ctx->scissor.SE_CLIP_RIGHT, clip_right);
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clip_bottom = MIN2(ctx->scissor.SE_CLIP_BOTTOM, clip_bottom);
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}
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/*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, clip_right);
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/*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, clip_bottom);
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}
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if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
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/*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL);
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}
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@ -47,6 +47,17 @@
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/* PE render targets must be aligned to 64 bytes */
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#define ETNA_PE_ALIGNMENT (64)
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/* These demarcate the margin (fixp16) between the computed sizes and the
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value sent to the chip. These have been set to the numbers used by the
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Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
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am not sure whether older hardware was relying on these or they were just a
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guess. But if so, these need to be moved to the _specs structure.
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*/
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#define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
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#define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
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#define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
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#define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
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/* GPU chip 3D specs */
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struct etna_specs {
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/* supports SUPERTILE (64x64) tiling? */
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@ -128,6 +139,8 @@ struct compiled_scissor_state {
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uint32_t SE_SCISSOR_TOP;
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uint32_t SE_SCISSOR_RIGHT;
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uint32_t SE_SCISSOR_BOTTOM;
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uint32_t SE_CLIP_RIGHT;
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uint32_t SE_CLIP_BOTTOM;
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};
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/* Compiled pipe_viewport_state */
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@ -142,6 +155,8 @@ struct compiled_viewport_state {
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uint32_t SE_SCISSOR_TOP;
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uint32_t SE_SCISSOR_RIGHT;
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uint32_t SE_SCISSOR_BOTTOM;
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uint32_t SE_CLIP_RIGHT;
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uint32_t SE_CLIP_BOTTOM;
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uint32_t PE_DEPTH_NEAR;
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uint32_t PE_DEPTH_FAR;
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};
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@ -164,6 +179,8 @@ struct compiled_framebuffer_state {
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uint32_t SE_SCISSOR_TOP;
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uint32_t SE_SCISSOR_RIGHT;
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uint32_t SE_SCISSOR_BOTTOM;
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uint32_t SE_CLIP_RIGHT;
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uint32_t SE_CLIP_BOTTOM;
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uint32_t RA_MULTISAMPLE_UNK00E04;
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uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
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uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
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@ -323,8 +323,10 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
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/* Scissor setup */
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cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
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cs->SE_SCISSOR_TOP = 0;
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cs->SE_SCISSOR_RIGHT = (sv->width << 16) - 1;
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cs->SE_SCISSOR_BOTTOM = (sv->height << 16) - 1;
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cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
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cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
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cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
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cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
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cs->TS_MEM_CONFIG = ts_mem_config;
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@ -345,13 +347,17 @@ etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
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{
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struct etna_context *ctx = etna_context(pctx);
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struct compiled_scissor_state *cs = &ctx->scissor;
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assert(ss->minx <= ss->maxx);
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assert(ss->miny <= ss->maxy);
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/* note that this state is only used when rasterizer_state->scissor is on */
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ctx->scissor_s = *ss;
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cs->SE_SCISSOR_LEFT = (ss->minx << 16);
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cs->SE_SCISSOR_TOP = (ss->miny << 16);
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cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) - 1;
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cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) - 1;
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cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
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cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
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cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
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cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
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ctx->dirty |= ETNA_DIRTY_SCISSOR;
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}
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@ -387,22 +393,14 @@ etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
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/* Compute scissor rectangle (fixp) from viewport.
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* Make sure left is always < right and top always < bottom.
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*/
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cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - vs->scale[0], 0.0f));
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cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - vs->scale[1], 0.0f));
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cs->SE_SCISSOR_RIGHT = etna_f32_to_fixp16(MAX2(vs->translate[0] + vs->scale[0], 0.0f));
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cs->SE_SCISSOR_BOTTOM = etna_f32_to_fixp16(MAX2(vs->translate[1] + vs->scale[1], 0.0f));
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if (cs->SE_SCISSOR_LEFT > cs->SE_SCISSOR_RIGHT) {
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uint32_t tmp = cs->SE_SCISSOR_RIGHT;
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cs->SE_SCISSOR_RIGHT = cs->SE_SCISSOR_LEFT;
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cs->SE_SCISSOR_LEFT = tmp;
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}
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if (cs->SE_SCISSOR_TOP > cs->SE_SCISSOR_BOTTOM) {
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uint32_t tmp = cs->SE_SCISSOR_BOTTOM;
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cs->SE_SCISSOR_BOTTOM = cs->SE_SCISSOR_TOP;
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cs->SE_SCISSOR_TOP = tmp;
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}
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cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
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cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
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uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
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uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
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cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
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cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
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cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
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cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
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cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
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cs->PE_DEPTH_FAR = fui(1.0);
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