i965: Support INTEL_DEBUG=clip to dump the clip program.

src/mesa/drivers/dri/i965/brw_clip.c

@@ -42,7 +42,6 @@
 #include "brw_state.h"
 #include "brw_clip.h"
 
-
 #define FRONT_UNFILLED_BIT  0x1
 #define BACK_UNFILLED_BIT   0x2
 
@@ -127,6 +126,13 @@ static void compile_clip_prog( struct brw_context *brw,
     */
    program = brw_get_program(&c.func, &program_size);
 
+    if (INTEL_DEBUG & DEBUG_CLIP) {
+      printf("clip:\n");
+      for (i = 0; i < program_size / sizeof(struct brw_instruction); i++)
+	 brw_disasm(stdout, &((struct brw_instruction *)program)[i]);
+      printf("\n");
+    }
+
    /* Upload
     */
    dri_bo_unreference(brw->clip.prog_bo);

src/mesa/drivers/dri/intel/intel_batchbuffer.c

@@ -276,7 +276,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
 {
    struct intel_context *intel = batch->intel;
 
-   if (intel->gen >= 4) {
+   if (0 && intel->gen >= 4) {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 		PIPE_CONTROL_INSTRUCTION_FLUSH |

src/mesa/drivers/dri/intel/intel_blit.c

@@ -353,6 +353,9 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
       OUT_BATCH(clear_val);
       ADVANCE_BATCH();
 
+      if (intel->always_flush_cache)
+	 intel_batchbuffer_emit_mi_flush(intel->batch);
+
       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
 	 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
       else

src/mesa/drivers/dri/intel/intel_context.c

@@ -487,6 +487,7 @@ static const struct dri_debug_control debug_control[] = {
    { "glsl_force", DEBUG_GLSL_FORCE },
    { "urb",   DEBUG_URB },
    { "vs",    DEBUG_VS },
+   { "clip",  DEBUG_CLIP },
    { NULL,    0 }
 };
 

src/mesa/drivers/dri/intel/intel_context.h

@@ -341,6 +341,7 @@ extern int INTEL_DEBUG;
 #define DEBUG_URB       0x1000000
 #define DEBUG_VS        0x2000000
 #define DEBUG_GLSL_FORCE 0x4000000
+#define DEBUG_CLIP      0x8000000
 
 #define DBG(...) do {						\
 	if (INTEL_DEBUG & FILE_DEBUG_FLAG)			\