radeonsi: don't execute LDS stores for TCS outputs that are never read
This is a per-component version of the previous mechanism. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>
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562b8c1a47
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@ -328,6 +328,7 @@ struct si_shader_info {
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ubyte output_semantic_name[PIPE_MAX_SHADER_OUTPUTS]; /**< TGSI_SEMANTIC_x */
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ubyte output_semantic_index[PIPE_MAX_SHADER_OUTPUTS];
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ubyte output_usagemask[PIPE_MAX_SHADER_OUTPUTS];
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ubyte output_readmask[PIPE_MAX_SHADER_OUTPUTS];
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ubyte output_streams[PIPE_MAX_SHADER_OUTPUTS];
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ubyte color_interpolate[2];
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@ -342,13 +343,6 @@ struct si_shader_info {
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uint num_memory_instructions; /**< sampler, buffer, and image instructions */
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/**
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* If a tessellation control shader reads outputs, this describes which ones.
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*/
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bool reads_pervertex_outputs;
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bool reads_perpatch_outputs;
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bool reads_tessfactor_outputs;
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ubyte colors_read; /**< which color components are read by the FS */
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ubyte colors_written;
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bool reads_samplemask; /**< does fragment shader read sample mask? */
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@ -518,7 +518,6 @@ static void si_nir_store_output_tcs(struct ac_shader_abi *abi, const struct nir_
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LLVMValueRef dw_addr, stride;
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LLVMValueRef buffer, base, addr;
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LLVMValueRef values[8];
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bool skip_lds_store;
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bool is_tess_factor = false, is_tess_inner = false;
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driver_location = driver_location / 4;
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@ -541,23 +540,16 @@ static void si_nir_store_output_tcs(struct ac_shader_abi *abi, const struct nir_
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dw_addr = get_tcs_out_current_patch_offset(ctx);
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dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr, vertex_index, param_index,
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name, index);
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skip_lds_store = !info->reads_pervertex_outputs;
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} else {
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dw_addr = get_tcs_out_current_patch_data_offset(ctx);
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dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr, vertex_index, param_index,
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name, index);
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skip_lds_store = !info->reads_perpatch_outputs;
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if (is_const && const_index == 0) {
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int name = info->output_semantic_name[driver_location];
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/* Always write tess factors into LDS for the TCS epilog. */
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if (name == TGSI_SEMANTIC_TESSINNER || name == TGSI_SEMANTIC_TESSOUTER) {
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/* The epilog doesn't read LDS if invocation 0 defines tess factors. */
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skip_lds_store = !info->reads_tessfactor_outputs &&
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ctx->shader->selector->info.tessfactors_are_def_in_all_invocs;
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is_tess_factor = true;
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is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
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}
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@ -585,7 +577,10 @@ static void si_nir_store_output_tcs(struct ac_shader_abi *abi, const struct nir_
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}
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/* Skip LDS stores if there is no LDS read of this output. */
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if (!skip_lds_store)
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if (info->output_readmask[driver_location + chan / 4] & (1 << (chan % 4)) ||
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/* The epilog reads LDS if invocation 0 doesn't define tess factors. */
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(is_tess_factor &&
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!ctx->shader->selector->info.tessfactors_are_def_in_all_invocs))
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lshs_lds_store(ctx, chan, dw_addr, value);
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value = ac_to_integer(&ctx->ac, value);
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@ -64,16 +64,18 @@ static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr
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}
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unsigned mask, bit_size;
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bool dual_slot;
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bool dual_slot, is_output_load;
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if (nir_intrinsic_infos[intr->intrinsic].index_map[NIR_INTRINSIC_WRMASK] > 0) {
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mask = nir_intrinsic_write_mask(intr); /* store */
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bit_size = nir_src_bit_size(intr->src[0]);
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dual_slot = bit_size == 64 && nir_src_num_components(intr->src[0]) >= 3;
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is_output_load = false;
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} else {
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mask = nir_ssa_def_components_read(&intr->dest.ssa); /* load */
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bit_size = intr->dest.ssa.bit_size;
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dual_slot = bit_size == 64 && intr->dest.ssa.num_components >= 3;
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is_output_load = !is_input;
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}
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/* Convert the 64-bit component mask to a 32-bit component mask. */
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@ -152,7 +154,15 @@ static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr
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info->output_semantic_name[loc] = name;
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info->output_semantic_index[loc] = index + i;
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if (slot_mask) {
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if (is_output_load) {
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/* Output loads have only a few things that we need to track. */
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info->output_readmask[loc] |= slot_mask;
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if (info->processor == PIPE_SHADER_FRAGMENT &&
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nir_intrinsic_io_semantics(intr).fb_fetch_output)
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info->uses_fbfetch = true;
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} else if (slot_mask) {
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/* Output stores. */
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if (info->processor == PIPE_SHADER_GEOMETRY) {
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unsigned gs_streams = (uint32_t)nir_intrinsic_io_semantics(intr).gs_streams <<
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(nir_intrinsic_component(intr) * 2);
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@ -418,28 +428,12 @@ static void scan_instruction(const struct nir_shader *nir, struct si_shader_info
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case nir_intrinsic_load_interpolated_input:
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scan_io_usage(info, intr, true);
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break;
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case nir_intrinsic_load_output:
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case nir_intrinsic_load_per_vertex_output:
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_per_vertex_output:
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scan_io_usage(info, intr, false);
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break;
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case nir_intrinsic_load_output: {
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unsigned location = nir_intrinsic_io_semantics(intr).location;
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if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
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if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
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location == VARYING_SLOT_TESS_LEVEL_OUTER)
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info->reads_tessfactor_outputs = true;
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else
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info->reads_perpatch_outputs = true;
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} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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if (nir_intrinsic_io_semantics(intr).fb_fetch_output)
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info->uses_fbfetch = true;
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}
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break;
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}
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case nir_intrinsic_load_per_vertex_output:
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info->reads_pervertex_outputs = true;
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break;
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case nir_intrinsic_load_deref:
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case nir_intrinsic_store_deref:
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case nir_intrinsic_interp_deref_at_centroid:
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@ -576,6 +570,10 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
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}
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}
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}
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/* Trim output read masks based on write masks. */
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for (unsigned i = 0; i < info->num_outputs; i++)
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info->output_readmask[i] &= info->output_usagemask[i];
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}
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static void si_nir_opts(struct nir_shader *nir, bool first)
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