v3dv: implement stencil testing
This works on combined depth/stencil formats only, separate stencil is not supported yet. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6766>
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@ -1736,6 +1736,12 @@ cmd_buffer_emit_graphics_pipeline(struct v3dv_cmd_buffer *cmd_buffer)
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cl_emit_prepacked(&job->bcl, &pipeline->cfg_bits);
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if (pipeline->emit_stencil_cfg[0]) {
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cl_emit_prepacked(&job->bcl, &pipeline->stencil_cfg[0]);
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if (pipeline->emit_stencil_cfg[1])
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cl_emit_prepacked(&job->bcl, &pipeline->stencil_cfg[1]);
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}
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/* FIXME: hardcoded values */
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cl_emit(&job->bcl, ZERO_ALL_FLAT_SHADE_FLAGS, flags);
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cl_emit(&job->bcl, ZERO_ALL_NON_PERSPECTIVE_FLAGS, flags);
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@ -976,6 +976,75 @@ pack_cfg_bits(struct v3dv_pipeline *pipeline,
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};
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}
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static uint32_t
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translate_stencil_op(enum pipe_stencil_op op)
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{
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switch (op) {
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case VK_STENCIL_OP_KEEP:
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return V3D_STENCIL_OP_KEEP;
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case VK_STENCIL_OP_ZERO:
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return V3D_STENCIL_OP_ZERO;
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case VK_STENCIL_OP_REPLACE:
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return V3D_STENCIL_OP_REPLACE;
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case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
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return V3D_STENCIL_OP_INCR;
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case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
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return V3D_STENCIL_OP_DECR;
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case VK_STENCIL_OP_INVERT:
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return V3D_STENCIL_OP_INVERT;
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case VK_STENCIL_OP_INCREMENT_AND_WRAP:
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return V3D_STENCIL_OP_INCWRAP;
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case VK_STENCIL_OP_DECREMENT_AND_WRAP:
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return V3D_STENCIL_OP_DECWRAP;
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default:
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unreachable("bad stencil op");
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}
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}
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static void
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pack_single_stencil_cfg(uint8_t *stencil_cfg,
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bool is_front,
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bool is_back,
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const VkStencilOpState *stencil_state)
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{
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v3dv_pack(stencil_cfg, STENCIL_CFG, config) {
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config.front_config = is_front;
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config.back_config = is_back;
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config.stencil_write_mask = stencil_state->writeMask;
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config.stencil_test_mask = stencil_state->compareMask;
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config.stencil_test_function = stencil_state->compareOp;
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config.stencil_pass_op = translate_stencil_op(stencil_state->passOp);
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config.depth_test_fail_op = translate_stencil_op(stencil_state->depthFailOp);
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config.stencil_test_fail_op = translate_stencil_op(stencil_state->failOp);
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config.stencil_ref_value = stencil_state->reference;
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}
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}
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static void
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pack_stencil_cfg(struct v3dv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *ds_info)
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{
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assert(sizeof(pipeline->stencil_cfg) == 2 * cl_packet_length(STENCIL_CFG));
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if (!ds_info || !ds_info->stencilTestEnable)
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return;
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/* If the front and back configurations are the same we can emit both with
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* a single packet.
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*/
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pipeline->emit_stencil_cfg[0] = true;
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if (memcmp(&ds_info->front, &ds_info->back, sizeof(ds_info->front)) == 0) {
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pack_single_stencil_cfg(pipeline->stencil_cfg[0],
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true, true, &ds_info->front);
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} else {
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pipeline->emit_stencil_cfg[1] = true;
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pack_single_stencil_cfg(pipeline->stencil_cfg[0],
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true, false, &ds_info->front);
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pack_single_stencil_cfg(pipeline->stencil_cfg[1],
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false, true, &ds_info->back);
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}
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}
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static void
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pack_shader_state_record(struct v3dv_pipeline *pipeline)
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{
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@ -1255,6 +1324,7 @@ pipeline_init(struct v3dv_pipeline *pipeline,
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raster_enabled ? pCreateInfo->pColorBlendState : NULL;
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pack_cfg_bits(pipeline, ds_info, rs_info, cb_info);
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pack_stencil_cfg(pipeline, ds_info);
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result = pipeline_compile_graphics(pipeline, pCreateInfo, alloc);
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@ -688,6 +688,10 @@ struct v3dv_pipeline {
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struct vpm_config vpm_cfg;
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struct vpm_config vpm_cfg_bin;
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/* If the pipeline should emit any of the stencil configuration packets */
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bool emit_stencil_cfg[2];
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/* Packets prepacked during pipeline creation
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*/
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uint8_t cfg_bits[cl_packet_length(CFG_BITS)];
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@ -695,6 +699,7 @@ struct v3dv_pipeline {
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uint8_t vcm_cache_size[cl_packet_length(VCM_CACHE_SIZE)];
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uint8_t vertex_attrs[cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD) *
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(MAX_VBS / 4)];
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uint8_t stencil_cfg[2][cl_packet_length(STENCIL_CFG)];
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};
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uint32_t v3dv_physical_device_api_version(struct v3dv_physical_device *dev);
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