KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

i965: Emit CS stall before MEDIA_VFE_STATE. 

This fixes hangs on GFXBench 5's Aztec Ruins benchmark.

Unfortunately, it regresses OglCSCloth performance by about 10%. There
are some ideas for fixing that.

The Vulkan driver already emits this stall.

Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke 2017-10-31 09:57:54 -07:00 committed by Matt Turner
parent bfe0f3a702
commit 55a97db523
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mesa/drivers/dri/i965/genX_state_upload.c
View File

@ -4169,6 +4169,18 @@ genX(upload_cs_state)(struct brw_context *brw)
uint32_t *bind = brw_state_batch(brw, prog_data->binding_table.size_bytes,
32, &stage_state->bind_bo_offset);
/* The MEDIA_VFE_STATE documentation for Gen8+ says:
*
* "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
* the only bits that are changed are scoreboard related: Scoreboard
* Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
* these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
*
* Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
* but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
*/
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
brw_batch_emit(brw, GENX(MEDIA_VFE_STATE), vfe) {
if (prog_data->total_scratch) {
uint32_t bo_offset;