freedreno/a5xx: refactor out helper for LRZ flush
Signed-off-by: Rob Clark <robdclark@gmail.com>
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@ -795,9 +795,6 @@ t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
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OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
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OUT_RING(ring, 0x00000012);
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OUT_RING(ring, 0x00000012);
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OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
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OUT_RING(ring, 0x00000000);
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OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
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OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
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OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
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OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
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A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
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A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
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@ -160,7 +160,22 @@ fd5_emit_render_cntl(struct fd_context *ctx, bool blit, bool binning)
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OUT_RING(ring, 0x00000008 | /* GRAS_SC_CNTL */
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OUT_RING(ring, 0x00000008 | /* GRAS_SC_CNTL */
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COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PASS) |
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COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PASS) |
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COND(samples_passed, A5XX_GRAS_SC_CNTL_SAMPLES_PASSED));
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COND(samples_passed, A5XX_GRAS_SC_CNTL_SAMPLES_PASSED));
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}
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static inline void
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fd5_emit_lrz_flush(struct fd_ringbuffer *ring)
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{
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/* TODO I think the extra writes to GRAS_LRZ_CNTL are probably
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* a workaround and not needed on all a5xx.
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*/
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OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
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OUT_RING(ring, A5XX_GRAS_LRZ_CNTL_ENABLE);
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, LRZ_FLUSH);
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OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
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OUT_RING(ring, 0x0);
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}
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}
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void fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit);
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void fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit);
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@ -348,8 +348,7 @@ fd5_emit_tile_init(struct fd_batch *batch)
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fd5_emit_restore(batch, ring);
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fd5_emit_restore(batch, ring);
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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fd5_emit_lrz_flush(ring);
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OUT_RING(ring, LRZ_FLUSH);
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_RING(ring, 0x0);
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OUT_RING(ring, 0x0);
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@ -629,8 +628,7 @@ fd5_emit_tile_fini(struct fd_batch *batch)
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_RING(ring, 0x0);
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OUT_RING(ring, 0x0);
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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fd5_emit_lrz_flush(ring);
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OUT_RING(ring, LRZ_FLUSH);
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fd5_cache_flush(batch, ring);
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fd5_cache_flush(batch, ring);
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fd5_set_render_mode(batch->ctx, ring, BYPASS);
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fd5_set_render_mode(batch->ctx, ring, BYPASS);
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@ -644,8 +642,7 @@ fd5_emit_sysmem_prep(struct fd_batch *batch)
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fd5_emit_restore(batch, ring);
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fd5_emit_restore(batch, ring);
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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fd5_emit_lrz_flush(ring);
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OUT_RING(ring, LRZ_FLUSH);
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_RING(ring, 0x0);
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OUT_RING(ring, 0x0);
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@ -719,8 +716,7 @@ fd5_emit_sysmem_fini(struct fd_batch *batch)
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
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OUT_RING(ring, 0x0);
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OUT_RING(ring, 0x0);
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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fd5_emit_lrz_flush(ring);
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OUT_RING(ring, LRZ_FLUSH);
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OUT_PKT7(ring, CP_EVENT_WRITE, 4);
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OUT_PKT7(ring, CP_EVENT_WRITE, 4);
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OUT_RING(ring, UNK_1D);
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OUT_RING(ring, UNK_1D);
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