intel/fs: Prevent emission of IR instructions not aligned to their own execution size.
This can occur during payload setup of SIMD-split send message instructions, which can lead to the emission of header setup instructions with a non-zero channel group and fixed SIMD width. Such instructions could end up using undefined channel enable signals except they don't care since they're always marked force_writemask_all. Not known to affect correctness of any workload at this point, but it would be trivial to back-port to stable if something comes up. Reported-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Sagar Ghuge <sagar.ghuge@intel.com>
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@ -114,11 +114,25 @@ namespace brw {
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fs_builder
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fs_builder
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group(unsigned n, unsigned i) const
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group(unsigned n, unsigned i) const
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{
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{
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assert(force_writemask_all ||
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(n <= dispatch_width() && i < dispatch_width() / n));
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fs_builder bld = *this;
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fs_builder bld = *this;
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if (n <= dispatch_width() && i < dispatch_width() / n) {
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bld._group += i * n;
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} else {
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/* The requested channel group isn't a subset of the channel group
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* of this builder, which means that the resulting instructions
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* would use (potentially undefined) channel enable signals not
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* specified by the parent builder. That's only valid if the
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* instruction doesn't have per-channel semantics, in which case
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* we should clear off the default group index in order to prevent
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* emitting instructions with channel group not aligned to their
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* own execution size.
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*/
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assert(force_writemask_all);
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bld._group = 0;
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}
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bld._dispatch_width = n;
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bld._dispatch_width = n;
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bld._group += i * n;
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return bld;
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return bld;
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}
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}
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