radeon/r200/r300: drop radeon renderbuffer private width/height
half stealing the code without taking the intel regions
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2ed3eddf9a
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54ee188a00
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@ -834,7 +834,7 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
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rImage->mt = NULL;
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}
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_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
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rb->width, rb->height, 1, 0, rb->cpp);
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rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
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texImage->RowStride = rb->pitch / rb->cpp;
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texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
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internalFormat,
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@ -866,8 +866,8 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
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t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB565].filter;
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break;
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}
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t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT)
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| ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT);
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t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
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| ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
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t->pp_txformat |= R200_TXFORMAT_NON_POWER2;
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t->pp_txpitch = pitch_val;
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t->pp_txpitch -= 32;
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@ -437,7 +437,7 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
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rImage->mt = NULL;
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}
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_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
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rb->width, rb->height, 1, 0, rb->cpp);
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rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
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texImage->RowStride = rb->pitch / rb->cpp;
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texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
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internalFormat,
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@ -473,15 +473,15 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
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break;
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}
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pitch_val--;
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t->pp_txsize = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) |
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((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT);
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t->pp_txsize = ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT) |
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((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT);
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t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
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t->pp_txpitch |= pitch_val;
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if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
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if (rb->width > 2048)
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if (rb->base.Width > 2048)
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t->pp_txpitch |= R500_TXWIDTH_BIT11;
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if (rb->height > 2048)
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if (rb->base.Height > 2048)
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t->pp_txpitch |= R500_TXHEIGHT_BIT11;
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}
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t->validated = GL_TRUE;
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@ -605,8 +605,8 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
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rb->cpp = buffers[i].cpp;
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rb->pitch = buffers[i].pitch;
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rb->width = drawable->w;
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rb->height = drawable->h;
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rb->base.Width = drawable->w;
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rb->base.Height = drawable->h;
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rb->has_surface = 0;
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if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
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@ -83,8 +83,6 @@ struct radeon_renderbuffer
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unsigned int cpp;
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/* unsigned int offset; */
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unsigned int pitch;
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unsigned int width;
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unsigned int height;
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uint32_t draw_offset; /* FBO */
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/* boo Xorg 6.8.2 compat */
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@ -706,7 +706,7 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_
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rImage->mt = NULL;
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}
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_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
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rb->width, rb->height, 1, 0, rb->cpp);
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rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
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texImage->RowStride = rb->pitch / rb->cpp;
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texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
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internalFormat,
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@ -738,8 +738,8 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_
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t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
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break;
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}
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t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT)
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| ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT);
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t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
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| ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
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t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
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t->pp_txpitch = pitch_val;
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t->pp_txpitch -= 32;
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