gallium/radeon: use gart_page_size instead of hardcoded 4096
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
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bfa8a00920
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544967faf5
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@ -58,7 +58,9 @@ static struct pipe_query *r300_create_query(struct pipe_context *pipe,
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else
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else
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q->num_pipes = r300screen->info.r300_num_gb_pipes;
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q->num_pipes = r300screen->info.r300_num_gb_pipes;
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q->buf = r300->rws->buffer_create(r300->rws, 4096, 4096,
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q->buf = r300->rws->buffer_create(r300->rws,
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r300screen->info.gart_page_size,
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r300screen->info.gart_page_size,
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RADEON_DOMAIN_GTT, 0);
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RADEON_DOMAIN_GTT, 0);
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if (!q->buf) {
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if (!q->buf) {
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FREE(q);
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FREE(q);
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@ -291,8 +291,9 @@ bool r600_common_context_init(struct r600_common_context *rctx,
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r600_query_init(rctx);
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r600_query_init(rctx);
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cayman_init_msaa(&rctx->b);
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cayman_init_msaa(&rctx->b);
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rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
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rctx->allocator_so_filled_size =
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0, PIPE_USAGE_DEFAULT, TRUE);
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u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
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4, 0, PIPE_USAGE_DEFAULT, TRUE);
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if (!rctx->allocator_so_filled_size)
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if (!rctx->allocator_so_filled_size)
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return false;
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return false;
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@ -845,8 +846,11 @@ static void r600_query_memory_info(struct pipe_screen *screen,
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struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
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struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
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const struct pipe_resource *templ)
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const struct pipe_resource *templ)
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{
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{
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struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
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if (templ->target == PIPE_BUFFER) {
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if (templ->target == PIPE_BUFFER) {
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return r600_buffer_create(screen, templ, 4096);
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return r600_buffer_create(screen, templ,
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rscreen->info.gart_page_size);
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} else {
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} else {
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return r600_texture_create(screen, templ);
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return r600_texture_create(screen, templ);
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}
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}
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@ -262,7 +262,8 @@ void r600_query_hw_destroy(struct r600_common_context *rctx,
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static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx,
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static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx,
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struct r600_query_hw *query)
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struct r600_query_hw *query)
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{
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{
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unsigned buf_size = MAX2(query->result_size, 4096);
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unsigned buf_size = MAX2(query->result_size,
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ctx->screen->info.gart_page_size);
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/* Queries are normally read by the CPU after
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/* Queries are normally read by the CPU after
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* being written by the gpu, hence staging is probably a good
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* being written by the gpu, hence staging is probably a good
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@ -598,7 +598,7 @@ static void si_dump_last_bo_list(struct si_context *sctx, FILE *f)
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for (i = 0; i < sctx->last_bo_count; i++) {
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for (i = 0; i < sctx->last_bo_count; i++) {
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/* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
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/* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
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const unsigned page_size = 4096;
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const unsigned page_size = sctx->b.screen->info.gart_page_size;
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uint64_t va = sctx->last_bo_list[i].vm_address;
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uint64_t va = sctx->last_bo_list[i].vm_address;
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uint64_t size = sctx->last_bo_list[i].buf->size;
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uint64_t size = sctx->last_bo_list[i].buf->size;
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bool hit = false;
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bool hit = false;
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@ -138,8 +138,8 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
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return NULL;
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return NULL;
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}
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}
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alloc_buffer.alloc_size = 4 * 1024;
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alloc_buffer.alloc_size = ctx->ws->info.gart_page_size;
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alloc_buffer.phys_alignment = 4 *1024;
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alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size;
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alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
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alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
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r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
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r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
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@ -201,6 +201,7 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
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static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
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static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
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struct amdgpu_cs_ib_info *info, unsigned ib_type)
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struct amdgpu_cs_ib_info *info, unsigned ib_type)
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{
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{
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struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
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/* Small IBs are better than big IBs, because the GPU goes idle quicker
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/* Small IBs are better than big IBs, because the GPU goes idle quicker
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* and there is less waiting for buffers and fences. Proof:
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* and there is less waiting for buffers and fences. Proof:
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* http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
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* http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
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@ -236,7 +237,7 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
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ib->used_ib_space = 0;
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ib->used_ib_space = 0;
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ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
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ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
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4096,
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aws->info.gart_page_size,
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RADEON_DOMAIN_GTT,
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RADEON_DOMAIN_GTT,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS);
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if (!ib->big_ib_buffer)
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if (!ib->big_ib_buffer)
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@ -779,7 +779,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
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memset(&args, 0, sizeof(args));
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memset(&args, 0, sizeof(args));
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args.addr = (uintptr_t)pointer;
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args.addr = (uintptr_t)pointer;
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args.size = align(size, sysconf(_SC_PAGE_SIZE));
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args.size = align(size, ws->info.gart_page_size);
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args.flags = RADEON_GEM_USERPTR_ANONONLY |
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args.flags = RADEON_GEM_USERPTR_ANONONLY |
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RADEON_GEM_USERPTR_VALIDATE |
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RADEON_GEM_USERPTR_VALIDATE |
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RADEON_GEM_USERPTR_REGISTER;
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RADEON_GEM_USERPTR_REGISTER;
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