iris: Disable SIMD32 when using a 16x MSAA framebuffer.
We weren't doing this documented workaround because it's sorta painful.
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@ -2390,6 +2390,10 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
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if (cso->samples != samples) {
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if (cso->samples != samples) {
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ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
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ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
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/* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
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if (GEN_GEN >= 9 && (cso->samples == 16 || samples == 16))
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ice->state.dirty |= IRIS_DIRTY_FS;
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}
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}
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if (cso->nr_cbufs != state->nr_cbufs) {
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if (cso->nr_cbufs != state->nr_cbufs) {
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@ -3689,9 +3693,7 @@ iris_store_fs_state(struct iris_context *ice,
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wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
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wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
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ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
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ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
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ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
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ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
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ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
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/* ps._32PixelDispatchEnable is filled in at draw time. */
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// XXX: Disable SIMD32 with 16x MSAA
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
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@ -4707,10 +4709,25 @@ iris_upload_dirty_render_state(struct iris_context *ice,
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}
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}
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#if GEN_GEN >= 9
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#if GEN_GEN >= 9
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if (stage == MESA_SHADER_FRAGMENT && wm_prog_data->uses_sample_mask) {
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if (stage == MESA_SHADER_FRAGMENT && wm_prog_data->uses_sample_mask) {
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uint32_t *shader_ps = (uint32_t *) shader->derived_data;
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uint32_t *shader_psx = shader_ps + GENX(3DSTATE_PS_length);
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uint32_t ps_state[GENX(3DSTATE_PS_length)] = {0};
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uint32_t psx_state[GENX(3DSTATE_PS_EXTRA_length)] = {0};
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uint32_t psx_state[GENX(3DSTATE_PS_EXTRA_length)] = {0};
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uint32_t *shader_psx = ((uint32_t*)shader->derived_data) +
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GENX(3DSTATE_PS_length);
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struct iris_rasterizer_state *cso = ice->state.cso_rast;
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struct iris_rasterizer_state *cso = ice->state.cso_rast;
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struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
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/* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
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*
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* "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
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* SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
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* mode."
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*
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* 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
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*/
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iris_pack_command(GENX(3DSTATE_PS), &ps_state, ps) {
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ps._32PixelDispatchEnable = wm_prog_data->dispatch_32 &&
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(cso_fb->samples != 16 || wm_prog_data->persample_dispatch);
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}
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iris_pack_command(GENX(3DSTATE_PS_EXTRA), &psx_state, psx) {
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iris_pack_command(GENX(3DSTATE_PS_EXTRA), &psx_state, psx) {
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if (wm_prog_data->post_depth_coverage)
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if (wm_prog_data->post_depth_coverage)
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@ -4721,8 +4738,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
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psx.InputCoverageMaskState = ICMS_NORMAL;
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psx.InputCoverageMaskState = ICMS_NORMAL;
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}
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}
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iris_batch_emit(batch, shader->derived_data,
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iris_emit_merge(batch, shader_ps, ps_state,
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sizeof(uint32_t) * GENX(3DSTATE_PS_length));
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GENX(3DSTATE_PS_length));
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iris_emit_merge(batch,
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iris_emit_merge(batch,
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shader_psx,
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shader_psx,
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psx_state,
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psx_state,
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