intel/fs: Implement the new load/store_scratch intrinsics
This commit fills in a number of different pieces: 1. We add support to brw_nir_lower_mem_access_bit_sizes to handle the new intrinsics. This involves simple plumbing work as well as a tiny bit of extra logic to always scalarize scratch intrinsics 2. Add code to brw_fs_nir.cpp to turn nir_load/store_scratch intrinsics into byte/dword scattered read/write messages which use the A32 stateless model. 3. Add code to lower_surface_logical_send to handle dword scattered messages and the A32 stateless model. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
parent
e2297699de
commit
53bfcdeecf
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@ -5368,6 +5368,15 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
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inst->opcode == SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL ||
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inst->opcode == SHADER_OPCODE_TYPED_ATOMIC_LOGICAL;
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const bool is_surface_access = is_typed_access ||
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inst->opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL ||
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inst->opcode == SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL ||
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inst->opcode == SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL;
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const bool is_stateless =
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surface.file == IMM && (surface.ud == BRW_BTI_STATELESS ||
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surface.ud == GEN8_BTI_STATELESS_NON_COHERENT);
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const bool has_side_effects = inst->has_side_effects();
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fs_reg sample_mask = has_side_effects ? bld.sample_mask_reg() :
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fs_reg(brw_imm_d(0xffff));
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@ -5381,25 +5390,63 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
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* we don't attempt to implement sample masks via predication for such
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* messages prior to Gen9, since we have to provide a header anyway. On
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* Gen11+ the header has been removed so we can only use predication.
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*
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* For all stateless A32 messages, we also need a header
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*/
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fs_reg header;
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if (devinfo->gen < 9 && is_typed_access) {
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if ((devinfo->gen < 9 && is_typed_access) || is_stateless) {
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fs_builder ubld = bld.exec_all().group(8, 0);
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header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
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ubld.MOV(header, brw_imm_d(0));
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ubld.group(1, 0).MOV(component(header, 7), sample_mask);
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if (is_stateless) {
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/* Both the typed and scattered byte/dword A32 messages take a buffer
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* base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
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* MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
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* for more details.) This is conveniently where the HW places the
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* scratch surface base address.
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*
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* From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
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*
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* "When a thread becomes 'active' it is allocated a portion of
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* scratch space, sized according to PerThreadScratchSpace. The
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* starting location of each thread’s scratch space allocation,
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* ScratchSpaceOffset, is passed in the thread payload in
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* R0.5[31:10] and is specified as a 1KB-granular offset from the
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* GeneralStateBaseAddress. The computation of ScratchSpaceOffset
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* includes the starting address of the stage’s scratch space
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* allocation, as programmed by ScratchSpaceBasePointer."
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*
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* The base address is passed in bits R0.5[31:10] and the bottom 10
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* bits of R0.5 are used for other things. Therefore, we have to
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* mask off the bottom 10 bits so that we don't get a garbage base
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* address.
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*/
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ubld.group(1, 0).AND(component(header, 5),
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retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
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brw_imm_ud(0xfffffc00));
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}
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if (is_surface_access)
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ubld.group(1, 0).MOV(component(header, 7), sample_mask);
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}
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const unsigned header_sz = header.file != BAD_FILE ? 1 : 0;
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fs_reg payload, payload2;
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unsigned mlen, ex_mlen = 0;
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if (devinfo->gen >= 9) {
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if (devinfo->gen >= 9 &&
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(src.file == BAD_FILE || header.file == BAD_FILE)) {
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/* We have split sends on gen9 and above */
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assert(header.file == BAD_FILE);
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payload = bld.move_to_vgrf(addr, addr_sz);
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payload2 = bld.move_to_vgrf(src, src_sz);
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mlen = addr_sz * (inst->exec_size / 8);
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ex_mlen = src_sz * (inst->exec_size / 8);
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if (header.file == BAD_FILE) {
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payload = bld.move_to_vgrf(addr, addr_sz);
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payload2 = bld.move_to_vgrf(src, src_sz);
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mlen = addr_sz * (inst->exec_size / 8);
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ex_mlen = src_sz * (inst->exec_size / 8);
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} else {
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assert(src.file == BAD_FILE);
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payload = header;
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payload2 = bld.move_to_vgrf(addr, addr_sz);
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mlen = header_sz;
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ex_mlen = addr_sz * (inst->exec_size / 8);
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}
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} else {
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/* Allocate space for the payload. */
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const unsigned sz = header_sz + addr_sz + src_sz;
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@ -5426,8 +5473,8 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
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/* Predicate the instruction on the sample mask if no header is
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* provided.
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*/
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if (header.file == BAD_FILE && sample_mask.file != BAD_FILE &&
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sample_mask.file != IMM) {
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if ((header.file == BAD_FILE || !is_surface_access) &&
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sample_mask.file != BAD_FILE && sample_mask.file != IMM) {
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const fs_builder ubld = bld.group(1, 0).exec_all();
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if (inst->predicate) {
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assert(inst->predicate == BRW_PREDICATE_NORMAL);
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@ -228,6 +228,9 @@ public:
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nir_intrinsic_instr *instr);
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fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg swizzle_nir_scratch_addr(const brw::fs_builder &bld,
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const fs_reg &addr,
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bool in_dwords);
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void nir_emit_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
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@ -341,6 +344,7 @@ public:
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int *push_constant_loc;
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fs_reg subgroup_id;
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fs_reg scratch_base;
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fs_reg frag_depth;
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fs_reg frag_stencil;
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fs_reg sample_mask;
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@ -2062,7 +2062,15 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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case SHADER_OPCODE_SEND:
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generate_send(inst, dst, src[0], src[1], src[2],
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inst->ex_mlen > 0 ? src[3] : brw_null_reg());
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send_count++;
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if ((inst->desc & 0xff) == BRW_BTI_STATELESS ||
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(inst->desc & 0xff) == GEN8_BTI_STATELESS_NON_COHERENT) {
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if (inst->size_written)
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fill_count++;
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else
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spill_count++;
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} else {
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send_count++;
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}
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break;
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case SHADER_OPCODE_GET_BUFFER_SIZE:
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@ -42,6 +42,7 @@ fs_visitor::emit_nir_code()
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nir_setup_outputs();
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nir_setup_uniforms();
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nir_emit_system_values();
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last_scratch = ALIGN(nir->scratch_size, 4) * dispatch_width;
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nir_emit_impl(nir_shader_get_entrypoint((nir_shader *)nir));
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}
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@ -4023,6 +4024,61 @@ image_intrinsic_coord_components(nir_intrinsic_instr *instr)
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}
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}
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/**
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* The offsets we get from NIR act as if each SIMD channel has it's own blob
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* of contiguous space. However, if we actually place each SIMD channel in
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* it's own space, we end up with terrible cache performance because each SIMD
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* channel accesses a different cache line even when they're all accessing the
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* same byte offset. To deal with this problem, we swizzle the address using
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* a simple algorithm which ensures that any time a SIMD message reads or
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* writes the same address, it's all in the same cache line. We have to keep
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* the bottom two bits fixed so that we can read/write up to a dword at a time
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* and the individual element is contiguous. We do this by splitting the
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* address as follows:
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*
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* 31 4-6 2 0
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* +-------------------------------+------------+----------+
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* | Hi address bits | chan index | addr low |
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* +-------------------------------+------------+----------+
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*
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* In other words, the bottom two address bits stay, and the top 30 get
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* shifted up so that we can stick the SIMD channel index in the middle. This
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* way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
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* at the same logical offset, the scratch read/write instruction acts on
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* continuous elements and we get good cache locality.
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*/
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fs_reg
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fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder &bld,
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const fs_reg &nir_addr,
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bool in_dwords)
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{
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const fs_reg &chan_index =
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nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION];
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const unsigned chan_index_bits = ffs(dispatch_width) - 1;
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fs_reg addr = bld.vgrf(BRW_REGISTER_TYPE_UD);
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if (in_dwords) {
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/* In this case, we know the address is aligned to a DWORD and we want
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* the final address in DWORDs.
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*/
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bld.SHL(addr, nir_addr, brw_imm_ud(chan_index_bits - 2));
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bld.OR(addr, addr, chan_index);
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} else {
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/* This case substantially more annoying because we have to pay
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* attention to those pesky two bottom bits.
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*/
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fs_reg addr_hi = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.AND(addr_hi, nir_addr, brw_imm_ud(~0x3u));
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bld.SHL(addr_hi, addr_hi, brw_imm_ud(chan_index_bits));
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fs_reg chan_addr = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.SHL(chan_addr, chan_index, brw_imm_ud(2));
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bld.AND(addr, nir_addr, brw_imm_ud(0x3u));
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bld.OR(addr, addr, addr_hi);
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bld.OR(addr, addr, chan_addr);
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}
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return addr;
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}
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void
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fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr)
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{
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break;
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}
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case nir_intrinsic_load_scratch: {
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assert(devinfo->gen >= 7);
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assert(nir_dest_num_components(instr->dest) == 1);
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const unsigned bit_size = nir_dest_bit_size(instr->dest);
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fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
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if (devinfo->gen >= 8) {
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srcs[SURFACE_LOGICAL_SRC_SURFACE] =
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brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT);
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} else {
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srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS);
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}
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srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
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const fs_reg nir_addr = get_nir_src(instr->src[0]);
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/* Make dest unsigned because that's what the temporary will be */
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dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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/* Read the vector */
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_bit_size(instr->dest) == 32);
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/* The offset for a DWORD scattered message is in dwords. */
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, true);
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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assert(nir_dest_bit_size(instr->dest) <= 32);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
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read_result, srcs, SURFACE_LOGICAL_NUM_SRCS);
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bld.MOV(dest, read_result);
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}
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break;
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}
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case nir_intrinsic_store_scratch: {
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assert(devinfo->gen >= 7);
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assert(nir_src_num_components(instr->src[0]) == 1);
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const unsigned bit_size = nir_src_bit_size(instr->src[0]);
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fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
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if (devinfo->gen >= 8) {
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srcs[SURFACE_LOGICAL_SRC_SURFACE] =
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brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT);
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} else {
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srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS);
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}
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srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
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const fs_reg nir_addr = get_nir_src(instr->src[1]);
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fs_reg data = get_nir_src(instr->src[0]);
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data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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assert(nir_intrinsic_write_mask(instr) ==
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(1u << instr->num_components) - 1);
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_bit_size(instr->src[0]) == 32);
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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/* The offset for a DWORD scattered message is in dwords. */
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, true);
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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}
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break;
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}
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case nir_intrinsic_load_subgroup_size:
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/* This should only happen for fragment shaders because every other case
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* is lowered in NIR so we can optimize on it.
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@ -77,8 +77,12 @@ static bool
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lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
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const struct gen_device_info *devinfo)
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{
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const bool needs_scalar =
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intrin->intrinsic == nir_intrinsic_load_scratch;
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assert(intrin->dest.is_ssa);
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if (intrin->dest.ssa.bit_size == 32)
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if (intrin->dest.ssa.bit_size == 32 &&
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(!needs_scalar || intrin->num_components == 1))
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return false;
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const unsigned bit_size = intrin->dest.ssa.bit_size;
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@ -119,7 +123,8 @@ lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
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} else {
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assert(load_offset % 4 == 0);
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load_bit_size = 32;
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load_comps = DIV_ROUND_UP(MIN2(bytes_left, 16), 4);
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load_comps = needs_scalar ? 1 :
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DIV_ROUND_UP(MIN2(bytes_left, 16), 4);
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}
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loads[num_loads++] = dup_mem_intrinsic(b, intrin, NULL, load_offset,
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@ -144,6 +149,9 @@ static bool
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lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
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const struct gen_device_info *devinfo)
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{
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const bool needs_scalar =
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intrin->intrinsic == nir_intrinsic_store_scratch;
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assert(intrin->src[0].is_ssa);
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nir_ssa_def *value = intrin->src[0].ssa;
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@ -159,7 +167,9 @@ lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
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assert(writemask < (1 << num_components));
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if ((value->bit_size <= 32 && num_components == 1) ||
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(value->bit_size == 32 && writemask == (1 << num_components) - 1))
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(value->bit_size == 32 &&
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writemask == (1 << num_components) - 1 &&
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!needs_scalar))
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return false;
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nir_src *offset_src = nir_get_io_offset_src(intrin);
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@ -180,7 +190,6 @@ lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
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while (BITSET_FFS(mask) != 0) {
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const int start = BITSET_FFS(mask) - 1;
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assert(start % byte_size == 0);
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int end;
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for (end = start + 1; end < bytes_written; end++) {
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@ -198,7 +207,7 @@ lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
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if (chunk_bytes >= 4 && is_dword_aligned) {
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store_align = MAX2(align, 4);
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store_bit_size = 32;
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store_comps = MIN2(chunk_bytes, 16) / 4;
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store_comps = needs_scalar ? 1 : MIN2(chunk_bytes, 16) / 4;
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} else {
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store_align = align;
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store_comps = 1;
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@ -208,7 +217,6 @@ lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
|
|||
store_bit_size = 16;
|
||||
}
|
||||
const unsigned store_bytes = store_comps * (store_bit_size / 8);
|
||||
assert(store_bytes % byte_size == 0);
|
||||
|
||||
nir_ssa_def *packed = nir_extract_bits(b, &value, 1, start * 8,
|
||||
store_comps, store_bit_size);
|
||||
|
@ -245,6 +253,7 @@ lower_mem_access_bit_sizes_impl(nir_function_impl *impl,
|
|||
case nir_intrinsic_load_global:
|
||||
case nir_intrinsic_load_ssbo:
|
||||
case nir_intrinsic_load_shared:
|
||||
case nir_intrinsic_load_scratch:
|
||||
if (lower_mem_load_bit_size(&b, intrin, devinfo))
|
||||
progress = true;
|
||||
break;
|
||||
|
@ -252,6 +261,7 @@ lower_mem_access_bit_sizes_impl(nir_function_impl *impl,
|
|||
case nir_intrinsic_store_global:
|
||||
case nir_intrinsic_store_ssbo:
|
||||
case nir_intrinsic_store_shared:
|
||||
case nir_intrinsic_store_scratch:
|
||||
if (lower_mem_store_bit_size(&b, intrin, devinfo))
|
||||
progress = true;
|
||||
break;
|
||||
|
@ -285,6 +295,12 @@ lower_mem_access_bit_sizes_impl(nir_function_impl *impl,
|
|||
* all nir load/store intrinsics into a series of either 8 or 32-bit
|
||||
* load/store intrinsics with a number of components that we can directly
|
||||
* handle in hardware and with a trivial write-mask.
|
||||
*
|
||||
* For scratch access, additional consideration has to be made due to the way
|
||||
* that we swizzle the memory addresses to achieve decent cache locality. In
|
||||
* particular, even though untyped surface read/write messages exist and work,
|
||||
* we can't use them to load multiple components in a single SEND. For more
|
||||
* detail on the scratch swizzle, see fs_visitor::swizzle_nir_scratch_addr.
|
||||
*/
|
||||
bool
|
||||
brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
|
||||
|
|
Loading…
Reference in New Issue