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i965: Rename define for the PIPE_CONTROL DC flush bit. 

Its previous name was somewhat misleading, this really behaves like a
RW cache flush rather than an invalidation.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2016-01-14 12:20:46 -08:00
parent 10d84ba9f0
commit 53739fddc6
5 changed files with 6 additions and 6 deletions
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2
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@ -919,7 +919,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
* MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
*/
const unsigned dc_flush =
brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_INVALIDATE : 0;
brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
if (brw->gen == 6) {
/* Hardware workaround: SNB B-Spec says:

2
src/mesa/drivers/dri/i965/brw_pipe_control.c
View File

@ -51,7 +51,7 @@ gen8_add_cs_stall_workaround_bits(uint32_t *flags)
PIPE_CONTROL_WRITE_TIMESTAMP |
PIPE_CONTROL_STALL_AT_SCOREBOARD |
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_DATA_CACHE_INVALIDATE;
PIPE_CONTROL_DATA_CACHE_FLUSH;
/* If we're doing a CS stall, and don't already have one of the
* workaround bits set, add "Stall at Pixel Scoreboard."

2
src/mesa/drivers/dri/i965/brw_program.c
View File

@ -209,7 +209,7 @@ static void
brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
{
struct brw_context *brw = brw_context(ctx);
unsigned bits = (PIPE_CONTROL_DATA_CACHE_INVALIDATE |
unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
assert(brw->gen >= 7 && brw->gen <= 9);

4
src/mesa/drivers/dri/i965/gen7_l3_state.c
View File

@ -333,7 +333,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
* which involves a first PIPE_CONTROL flush which stalls the pipeline...
*/
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_INVALIDATE |
PIPE_CONTROL_DATA_CACHE_FLUSH |
PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
@ -362,7 +362,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
* complete when the L3 configuration registers are modified.
*/
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_INVALIDATE |
PIPE_CONTROL_DATA_CACHE_FLUSH |
PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);

2
src/mesa/drivers/dri/i965/intel_reg.h
View File

@ -86,7 +86,7 @@
#define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8)
#define PIPE_CONTROL_FLUSH_ENABLE (1 << 7) /* Gen7+ only */
/* GT */
#define PIPE_CONTROL_DATA_CACHE_INVALIDATE (1 << 5)
#define PIPE_CONTROL_DATA_CACHE_FLUSH (1 << 5)
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4)
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3)
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2)