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i965/fs: Add support for translating ir_triop_fma into MAD. 

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Matt Turner 2013-04-23 17:32:26 -07:00
parent e817b94a2c
commit 530842127e
4 changed files with 10 additions and 0 deletions
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1
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -179,6 +179,7 @@ ALU3(BFI2)
ALU1(FBH)
ALU1(FBL)
ALU1(CBIT)
ALU3(MAD)
/** Gen4 predicated IF. */
fs_inst *

1
src/mesa/drivers/dri/i965/brw_fs.h
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@ -285,6 +285,7 @@ public:
fs_inst *FBH(fs_reg dst, fs_reg value);
fs_inst *FBL(fs_reg dst, fs_reg value);
fs_inst *CBIT(fs_reg dst, fs_reg value);
fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,

1
src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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@ -360,6 +360,7 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
assert(!"not yet supported");
break;
case ir_triop_fma:
case ir_triop_lrp:
case ir_triop_bitfield_extract:
for (i = 0; i < vector_elements; i++) {

7
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
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@ -718,6 +718,13 @@ fs_visitor::visit(ir_expression *ir)
break;
}
case ir_triop_fma:
/* Note that the instruction's argument order is reversed from GLSL
* and the IR.
*/
emit(MAD(this->result, op[2], op[1], op[0]));
break;
case ir_triop_lrp:
emit_lrp(this->result, op[0], op[1], op[2]);
break;