From 52172fded5640d5f6257766275a7b4cf01ce7017 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sat, 27 Feb 2021 18:24:44 -0500 Subject: [PATCH] nv50/ir: fix emission of cas without a destination We were previously dumping $r127 in there. This has a bad effect on nv50, so make sure we allocate an actual register for it, even if there's nothing using the result. Signed-off-by: Ilia Mirkin Acked-by: Pierre Moreau Part-of: --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 ++++- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 7 +++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 6da706b79b1..9120f99c8c6 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp @@ -3928,7 +3928,10 @@ DeadCodeElim::visit(BasicBlock *bb) if (i->op == OP_ATOM || i->op == OP_SUREDP || i->op == OP_SUREDB) { - i->setDef(0, NULL); + const Target *targ = prog->getTarget(); + if (targ->getChipset() >= NVISA_GF100_CHIPSET || + i->subOp != NV50_IR_SUBOP_ATOM_CAS) + i->setDef(0, NULL); if (i->op == OP_ATOM && i->subOp == NV50_IR_SUBOP_ATOM_EXCH) { i->cache = CACHE_CV; i->op = OP_STORE; diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 20c6acadc17..6a6ad01ce40 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -2574,6 +2574,13 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb) i->op == OP_MERGE || i->op == OP_SPLIT) { constrList.push_back(i); + } else + if (i->op == OP_ATOM && i->subOp == NV50_IR_SUBOP_ATOM_CAS && + targ->getChipset() < 0xc0) { + // Like a hazard, but for a def. + Instruction *nop = new_Instruction(func, OP_NOP, i->dType); + nop->setSrc(0, i->getDef(0)); + i->bb->insertAfter(i, nop); } } return true;