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freedreno: Replace OUT_RELOCW with OUT_RELOC. 

Final cleanup commit now that they're the same.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>
This commit is contained in:
Eric Anholt 2020-05-08 12:39:36 -07:00 committed by Marge Bot
parent 064f395a89
commit 51d7a71bd4
28 changed files with 98 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/freedreno/computerator/a6xx.c
View File

@ -258,7 +258,7 @@ cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
A6XX_IBO_2_UNK4 | A6XX_IBO_2_UNK31 |
A6XX_IBO_2_TYPE(A6XX_TEX_1D));
OUT_RING(state, A6XX_IBO_3_ARRAY_PITCH(0));
OUT_RELOCW(state, kernel->bufs[i], 0, 0, 0);
OUT_RELOC(state, kernel->bufs[i], 0, 0, 0);
OUT_RING(state, 0x00000000);
OUT_RING(state, 0x00000000);
OUT_RING(state, 0x00000000);
@ -300,7 +300,7 @@ event_write(struct fd_ringbuffer *ring, struct kernel *kernel,
struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
seqno = ++a6xx_backend->seqno;
OUT_RELOCW(ring, control_ptr(a6xx_backend, seqno)); /* ADDR_LO/HI */
OUT_RELOC(ring, control_ptr(a6xx_backend, seqno)); /* ADDR_LO/HI */
OUT_RING(ring, seqno);
}
@ -398,7 +398,7 @@ a6xx_emit_grid(struct kernel *kernel, uint32_t grid[3], struct fd_submit *submit
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_64B |
CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
OUT_RELOCW(ring, query_sample_idx(a6xx_backend, i, start));
OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, start));
}
}
@ -418,7 +418,7 @@ a6xx_emit_grid(struct kernel *kernel, uint32_t grid[3], struct fd_submit *submit
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_64B |
CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
OUT_RELOCW(ring, query_sample_idx(a6xx_backend, i, stop));
OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, stop));
}
/* and compute the result: */
@ -427,7 +427,7 @@ a6xx_emit_grid(struct kernel *kernel, uint32_t grid[3], struct fd_submit *submit
OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
CP_MEM_TO_MEM_0_NEG_C);
OUT_RELOCW(ring, query_sample_idx(a6xx_backend, i, result)); /* dst */
OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, result)); /* dst */
OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, result)); /* srcA */
OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, stop)); /* srcB */
OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, start)); /* srcC */

2
src/freedreno/drm/freedreno_ringbuffer.h
View File

@ -255,8 +255,6 @@ OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
});
}
#define OUT_RELOCW OUT_RELOC
static inline void
OUT_RB(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
{

6
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
View File

@ -109,7 +109,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
OUT_RING(ring, pitch >> 5); /* RB_COPY_DEST_PITCH */
OUT_RING(ring, /* RB_COPY_DEST_INFO */
A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(format)) |
@ -452,7 +452,7 @@ fd2_emit_sysmem_prep(struct fd_batch *batch)
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
OUT_RELOCW(ring, rsc->bo, offset,
OUT_RELOC(ring, rsc->bo, offset,
COND(!rsc->layout.tile_mode, A2XX_RB_COLOR_INFO_LINEAR) |
A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)), 0);
@ -601,7 +601,7 @@ fd2_emit_tile_init(struct fd_batch *batch)
* .z: 0x4B00D000 (?)
* .w: 0x4B000000 (?) | max_index (?)
*/
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0x40000000, -2);
OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0x40000000, -2);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x4B00D000);
OUT_RING(ring, 0x4B000000 | bo_size);

4
src/gallium/drivers/freedreno/a2xx/fd2_query.c
View File

@ -107,7 +107,7 @@ perfcntr_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT3(ring, CP_REG_TO_MEM, 2);
OUT_RING(ring, counter->counter_reg_lo | CP_REG_TO_MEM_0_ACCUMULATE);
OUT_RELOCW(ring, query_sample_idx(aq, i, start));
OUT_RELOC(ring, query_sample_idx(aq, i, start));
}
}
@ -134,7 +134,7 @@ perfcntr_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT3(ring, CP_REG_TO_MEM, 2);
OUT_RING(ring, counter->counter_reg_lo | CP_REG_TO_MEM_0_ACCUMULATE);
OUT_RELOCW(ring, query_sample_idx(aq, i, stop));
OUT_RELOC(ring, query_sample_idx(aq, i, stop));
}
}

2
src/gallium/drivers/freedreno/a3xx/fd3_emit.c
View File

@ -112,7 +112,7 @@ fd3_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean writ
for (i = 0; i < num; i++) {
if (prscs[i]) {
if (write) {
OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
} else {
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
}

16
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
View File

@ -116,7 +116,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
if (bin_w || (i >= nr_bufs) || !bufs[i]) {
OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
} else {
OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
OUT_RELOC(ring, rsc->bo, offset, 0, -1);
}
OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
@ -183,7 +183,7 @@ emit_binning_workaround(struct fd_batch *batch)
OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
A3XX_RB_COPY_CONTROL_MODE(0) |
A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
OUT_RELOCW(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
OUT_RELOC(ring, fd_resource(ctx->solid_vbuf)->bo, 0x20, 0, -1); /* RB_COPY_DEST_BASE */
OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
@ -341,7 +341,7 @@ emit_gmem2mem_surf(struct fd_batch *batch,
format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
OUT_RELOCW(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
OUT_RELOC(ring, rsc->bo, offset, 0, -1); /* RB_COPY_DEST_BASE */
OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch));
OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
@ -558,7 +558,7 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
OUT_PKT3(ring, CP_MEM_WRITE, 5);
OUT_RELOCW(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
OUT_RELOC(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
OUT_RING(ring, fui(x0));
OUT_RING(ring, fui(y0));
OUT_RING(ring, fui(x1));
@ -772,7 +772,7 @@ update_vsc_pipe(struct fd_batch *batch)
int i;
OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
for (i = 0; i < 8; i++) {
const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
@ -787,7 +787,7 @@ update_vsc_pipe(struct fd_batch *batch)
A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
A3XX_VSC_PIPE_CONFIG_H(pipe->h));
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE[i].DATA_ADDRESS */
OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE[i].DATA_LENGTH */
}
}
@ -1024,8 +1024,8 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
OUT_RELOCW(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
OUT_RELOC(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
(tile->p * 4), 0, 0);
} else {
OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);

6
src/gallium/drivers/freedreno/a4xx/fd4_emit.c
View File

@ -107,7 +107,7 @@ fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean writ
for (i = 0; i < num; i++) {
if (prscs[i]) {
if (write) {
OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
} else {
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
}
@ -949,8 +949,8 @@ fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
for (i = 0; i < sizedwords; i++) {
OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
OUT_RING(ring, 0x00000000);
OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
OUT_RELOC (ring, src_bo, src_off, 0, 0);
OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
OUT_RELOC(ring, src_bo, src_off, 0, 0);
dst_off += 4;
src_off += 4;

14
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
View File

@ -119,7 +119,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
OUT_RING(ring, base);
OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
} else {
OUT_RELOCW(ring, rsc->bo, offset, 0, 0);
OUT_RELOC(ring, rsc->bo, offset, 0, 0);
/* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
* not sure if we need to skip it for bypass or
* not.
@ -174,7 +174,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, bool stencil,
OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch));
OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
@ -349,7 +349,7 @@ fd4_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
OUT_PKT3(ring, CP_MEM_WRITE, 5);
OUT_RELOCW(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
OUT_RELOC(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
OUT_RING(ring, fui(x0));
OUT_RING(ring, fui(y0));
OUT_RING(ring, fui(x1));
@ -559,7 +559,7 @@ update_vsc_pipe(struct fd_batch *batch)
int i;
OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
OUT_RELOC(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
for (i = 0; i < 8; i++) {
@ -576,7 +576,7 @@ update_vsc_pipe(struct fd_batch *batch)
ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
}
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
}
OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
@ -770,8 +770,8 @@ fd4_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
A4XX_PC_VSTREAM_CONTROL_N(tile->n));
OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
OUT_RELOCW(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
OUT_RELOC(ring, pipe_bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
OUT_RELOC(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
(tile->p * 4), 0, 0);
} else {
OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);

6
src/gallium/drivers/freedreno/a4xx/fd4_query.c
View File

@ -167,7 +167,7 @@ time_elapsed_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_RING(ring, CP_REG_TO_MEM_0_REG(REG_A4XX_RBBM_PERFCTR_CP_0_LO) |
CP_REG_TO_MEM_0_64B |
CP_REG_TO_MEM_0_CNT(2)); /* write 2 regs to mem */
OUT_RELOCW(ring, scratch_bo, sample_off, 0, 0);
OUT_RELOC(ring, scratch_bo, sample_off, 0, 0);
/* ok... here we really *would* like to use the CP_SET_CONSTANT
* mode which can add a constant to value in reg2 and write to
@ -181,7 +181,7 @@ time_elapsed_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring)
/* per-sample offset to scratch bo: */
OUT_PKT3(ring, CP_MEM_WRITE, 2);
OUT_RELOCW(ring, scratch_bo, addr_off, 0, 0);
OUT_RELOC(ring, scratch_bo, addr_off, 0, 0);
OUT_RING(ring, samp->offset);
/* now add to that the per-tile base: */
@ -189,7 +189,7 @@ time_elapsed_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_RING(ring, CP_REG_TO_MEM_0_REG(HW_QUERY_BASE_REG) |
CP_REG_TO_MEM_0_ACCUMULATE |
CP_REG_TO_MEM_0_CNT(0)); /* readback 1 regs */
OUT_RELOCW(ring, scratch_bo, addr_off, 0, 0);
OUT_RELOC(ring, scratch_bo, addr_off, 0, 0);
/* now copy that back to CP_ME_NRT_ADDR: */
OUT_PKT3(ring, CP_MEM_TO_REG, 2);

4
src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
View File

@ -289,7 +289,7 @@ emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
A5XX_RB_2D_DST_INFO_TILE_MODE(TILE5_LINEAR) |
A5XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(p) |
A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(128));
OUT_RING(ring, 0x00000000);
@ -419,7 +419,7 @@ emit_blit(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
A5XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
A5XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(dpitch) |
A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(dsize));
OUT_RING(ring, 0x00000000);

2
src/gallium/drivers/freedreno/a5xx/fd5_compute.c
View File

@ -211,7 +211,7 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
OUT_PKT7(ring, CP_NOP, 2 * nglobal);
foreach_bit(i, ctx->global_bindings.enabled_mask) {
struct pipe_resource *prsc = ctx->global_bindings.buf[i];
OUT_RELOCW(ring, fd_resource(prsc)->bo, 0, 0, 0);
OUT_RELOC(ring, fd_resource(prsc)->bo, 0, 0, 0);
}
}

2
src/gallium/drivers/freedreno/a5xx/fd5_context.h
View File

@ -95,7 +95,7 @@ fd5_emit_flush(struct fd_context *ctx, struct fd_ringbuffer *ring)
{
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CACHE_FLUSH_TS);
OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RELOC(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RING(ring, 0x00000000);
OUT_WFI5(ring);

2
src/gallium/drivers/freedreno/a5xx/fd5_draw.c
View File

@ -229,7 +229,7 @@ fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0);
OUT_RELOC(ring, zsbuf->lrz, 0x1000, 0, 0);
OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
OUT_RING(ring, 0x00000000);

12
src/gallium/drivers/freedreno/a5xx/fd5_emit.c
View File

@ -112,7 +112,7 @@ fd5_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean writ
for (i = 0; i < num; i++) {
if (prscs[i]) {
if (write) {
OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
} else {
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
}
@ -468,7 +468,7 @@ emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
if (buf->buffer) {
struct fd_resource *rsc = fd_resource(buf->buffer);
OUT_RELOCW(ring, rsc->bo, buf->buffer_offset, 0, 0);
OUT_RELOC(ring, rsc->bo, buf->buffer_offset, 0, 0);
} else {
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
@ -740,7 +740,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
/* VPC_SO[i].BUFFER_BASE_LO: */
OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
OUT_RELOC(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
OUT_RING(ring, target->buffer_size + offset);
OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
@ -749,7 +749,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
// TODO just give hw a dummy addr for now.. we should
// be using this an then CP_MEM_TO_REG to set the
// VPC_SO[i].BUFFER_OFFSET for the next draw..
OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
OUT_RELOC(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
emit->streamout_mask |= (1 << i);
}
@ -1143,8 +1143,8 @@ fd5_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
for (i = 0; i < sizedwords; i++) {
OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
OUT_RING(ring, 0x00000000);
OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
OUT_RELOC (ring, src_bo, src_off, 0, 0);
OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
OUT_RELOC(ring, src_bo, src_off, 0, 0);
dst_off += 4;
src_off += 4;

2
src/gallium/drivers/freedreno/a5xx/fd5_emit.h
View File

@ -139,7 +139,7 @@ fd5_emit_blit(struct fd_context *ctx, struct fd_ringbuffer *ring)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(BLIT));
OUT_RELOCW(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RELOC(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RING(ring, 0x00000000);
emit_marker5(ring, 7);

20
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
View File

@ -109,7 +109,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */
} else {
debug_assert((offset + size) <= fd_bo_size(rsc->bo));
OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
}
OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
@ -155,7 +155,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
OUT_RING(ring, gmem->zsbuf_base[0]); /* RB_DEPTH_BUFFER_BASE_LO */
OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
} else {
OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
OUT_RELOC(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
}
OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_PITCH(stride));
OUT_RING(ring, A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
@ -170,11 +170,11 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
if (rsc->lrz) {
OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
OUT_RELOCW(ring, rsc->lrz, 0x1000, 0, 0);
OUT_RELOC(ring, rsc->lrz, 0x1000, 0, 0);
OUT_RING(ring, A5XX_GRAS_LRZ_BUFFER_PITCH(rsc->lrz_pitch));
OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
OUT_RELOC(ring, rsc->lrz, 0, 0, 0);
} else {
OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
OUT_RING(ring, 0x00000000);
@ -202,7 +202,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
OUT_RING(ring, gmem->zsbuf_base[1]); /* RB_STENCIL_BASE_LO */
OUT_RING(ring, 0x00000000); /* RB_STENCIL_BASE_HI */
} else {
OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
OUT_RELOC(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
}
OUT_RING(ring, A5XX_RB_STENCIL_PITCH(stride));
OUT_RING(ring, A5XX_RB_STENCIL_ARRAY_PITCH(size));
@ -269,7 +269,7 @@ update_vsc_pipe(struct fd_batch *batch)
OUT_PKT4(ring, REG_A5XX_VSC_BIN_SIZE, 3);
OUT_RING(ring, A5XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
A5XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
OUT_RELOCW(ring, fd5_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
OUT_RELOC(ring, fd5_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
OUT_PKT4(ring, REG_A5XX_UNKNOWN_0BC5, 2);
OUT_RING(ring, 0x00000000); /* UNKNOWN_0BC5 */
@ -290,7 +290,7 @@ update_vsc_pipe(struct fd_batch *batch)
ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x20000,
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
}
OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
}
OUT_PKT4(ring, REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
@ -351,7 +351,7 @@ emit_binning_pass(struct fd_batch *batch)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CACHE_FLUSH_TS);
OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RELOC(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RING(ring, 0x00000000);
// TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??)
@ -634,7 +634,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
OUT_RING(ring, 0x00000004 | /* XXX RB_RESOLVE_CNTL_3 */
COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED));
OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch));
OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
@ -776,7 +776,7 @@ fd5_emit_sysmem_fini(struct fd_batch *batch)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, PC_CCU_FLUSH_COLOR_TS);
OUT_RELOCW(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RELOC(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RING(ring, 0x00000000);
}

2
src/gallium/drivers/freedreno/a5xx/fd5_image.c
View File

@ -184,7 +184,7 @@ static void emit_image_ssbo(struct fd_ringbuffer *ring, unsigned slot,
CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
if (img->bo) {
OUT_RELOCW(ring, img->bo, img->offset, 0, 0);
OUT_RELOC(ring, img->bo, img->offset, 0, 0);
} else {
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);

20
src/gallium/drivers/freedreno/a5xx/fd5_query.c
View File

@ -66,7 +66,7 @@ occlusion_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_RING(ring, A5XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
OUT_RELOCW(ring, query_sample(aq, start));
OUT_RELOC(ring, query_sample(aq, start));
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, ZPASS_DONE);
@ -81,7 +81,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch)
struct fd_ringbuffer *ring = batch->draw;
OUT_PKT7(ring, CP_MEM_WRITE, 4);
OUT_RELOCW(ring, query_sample(aq, stop));
OUT_RELOC(ring, query_sample(aq, stop));
OUT_RING(ring, 0xffffffff);
OUT_RING(ring, 0xffffffff);
@ -91,7 +91,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_RING(ring, A5XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
OUT_RELOCW(ring, query_sample(aq, stop));
OUT_RELOC(ring, query_sample(aq, stop));
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, ZPASS_DONE);
@ -108,7 +108,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
CP_MEM_TO_MEM_0_NEG_C);
OUT_RELOCW(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* srcA */
OUT_RELOC(ring, query_sample(aq, stop)); /* srcB */
OUT_RELOC(ring, query_sample(aq, start)); /* srcC */
@ -168,7 +168,7 @@ timestamp_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS) |
CP_EVENT_WRITE_0_TIMESTAMP);
OUT_RELOCW(ring, query_sample(aq, start));
OUT_RELOC(ring, query_sample(aq, start));
OUT_RING(ring, 0x00000000);
fd_reset_wfi(batch);
@ -182,7 +182,7 @@ timestamp_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS) |
CP_EVENT_WRITE_0_TIMESTAMP);
OUT_RELOCW(ring, query_sample(aq, stop));
OUT_RELOC(ring, query_sample(aq, stop));
OUT_RING(ring, 0x00000000);
fd_reset_wfi(batch);
@ -192,7 +192,7 @@ timestamp_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
CP_MEM_TO_MEM_0_NEG_C);
OUT_RELOCW(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* srcA */
OUT_RELOC(ring, query_sample(aq, stop)); /* srcB */
OUT_RELOC(ring, query_sample(aq, start)); /* srcC */
@ -305,7 +305,7 @@ perfcntr_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_64B |
CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
OUT_RELOCW(ring, query_sample_idx(aq, i, start));
OUT_RELOC(ring, query_sample_idx(aq, i, start));
}
}
@ -333,7 +333,7 @@ perfcntr_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_64B |
CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
OUT_RELOCW(ring, query_sample_idx(aq, i, stop));
OUT_RELOC(ring, query_sample_idx(aq, i, stop));
}
/* and compute the result: */
@ -342,7 +342,7 @@ perfcntr_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
CP_MEM_TO_MEM_0_NEG_C);
OUT_RELOCW(ring, query_sample_idx(aq, i, result)); /* dst */
OUT_RELOC(ring, query_sample_idx(aq, i, result)); /* dst */
OUT_RELOC(ring, query_sample_idx(aq, i, result)); /* srcA */
OUT_RELOC(ring, query_sample_idx(aq, i, stop)); /* srcB */
OUT_RELOC(ring, query_sample_idx(aq, i, start)); /* srcC */

4
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View File

@ -287,7 +287,7 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p));
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
@ -528,7 +528,7 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap) |
COND(util_format_is_srgb(info->dst.format), A6XX_RB_2D_DST_INFO_SRGB) |
COND(dubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dslice->pitch));
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);

2
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
View File

@ -156,7 +156,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
OUT_PKT7(ring, CP_NOP, 2 * nglobal);
foreach_bit(i, ctx->global_bindings.enabled_mask) {
struct pipe_resource *prsc = ctx->global_bindings.buf[i];
OUT_RELOCW(ring, fd_resource(prsc)->bo, 0, 0, 0);
OUT_RELOC(ring, fd_resource(prsc)->bo, 0, 0, 0);
}
}

2
src/gallium/drivers/freedreno/a6xx/fd6_const.c
View File

@ -125,7 +125,7 @@ fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean writ
for (i = 0; i < num; i++) {
if (prscs[i]) {
if (write) {
OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
} else {
OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
}

2
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
View File

@ -410,7 +410,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_16_UNORM) |
A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
OUT_RELOCW(ring, zsbuf->lrz, 0, 0, 0);
OUT_RELOC(ring, zsbuf->lrz, 0, 0, 0);
OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);

8
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View File

@ -671,7 +671,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3
OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
/* VPC_SO[i].BUFFER_BASE_LO: */
OUT_RELOCW(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
OUT_RELOC(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
OUT_RING(ring, target->buffer_size - target->buffer_offset);
if (so->reset & (1 << i)) {
@ -687,7 +687,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3
}
OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
OUT_RELOCW(ring, control_ptr(fd6_context(ctx), flush_base[i]));
OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i]));
so->reset &= ~(1 << i);
@ -1187,8 +1187,8 @@ fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
for (i = 0; i < sizedwords; i++) {
OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
OUT_RING(ring, 0x00000000);
OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
OUT_RELOC (ring, src_bo, src_off, 0, 0);
OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
OUT_RELOC(ring, src_bo, src_off, 0, 0);
dst_off += 4;
src_off += 4;

2
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
View File

@ -158,7 +158,7 @@ fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
if (timestamp) {
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
seqno = ++fd6_ctx->seqno;
OUT_RELOCW(ring, control_ptr(fd6_ctx, seqno)); /* ADDR_LO/HI */
OUT_RELOC(ring, control_ptr(fd6_ctx, seqno)); /* ADDR_LO/HI */
OUT_RING(ring, seqno);
}

16
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View File

@ -58,7 +58,7 @@ fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
int level, int layer)
{
if (fd_resource_ubwc_enabled(rsc, level)) {
OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
OUT_RELOC(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
OUT_RING(ring,
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
@ -421,7 +421,7 @@ emit_vsc_overflow_test(struct fd_batch *batch)
/* Clear vsc_scratch: */
OUT_PKT7(ring, CP_MEM_WRITE, 3);
OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));
OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch));
OUT_RING(ring, 0x0);
/* Check for overflow, write vsc_scratch if detected: */
@ -433,7 +433,7 @@ emit_vsc_overflow_test(struct fd_batch *batch)
OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_draw_strm_pitch));
OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_draw_strm_pitch));
OUT_PKT7(ring, CP_COND_WRITE5, 8);
@ -443,7 +443,7 @@ emit_vsc_overflow_test(struct fd_batch *batch)
OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_prim_strm_pitch));
OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_prim_strm_pitch));
}
@ -487,7 +487,7 @@ emit_vsc_overflow_test(struct fd_batch *batch)
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
CP_REG_TO_MEM_0_CNT(1 - 1));
OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_overflow));
OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow));
OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
OUT_RING(ring, 0x0);
@ -1461,11 +1461,11 @@ setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
OUT_RELOCW(ring, batch->tessfactor_bo, 0, 0, 0);
OUT_RELOC(ring, batch->tessfactor_bo, 0, 0, 0);
batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
OUT_RELOCW(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
OUT_RELOCW(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
OUT_RELOC(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
OUT_RELOC(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
}
static void

4
src/gallium/drivers/freedreno/a6xx/fd6_image.c
View File

@ -262,7 +262,7 @@ static void emit_image_ssbo(struct fd_ringbuffer *ring, struct fd6_image *img)
OUT_RING(ring, A6XX_IBO_3_ARRAY_PITCH(img->array_pitch) |
COND(ubwc_enabled, A6XX_IBO_3_FLAG | A6XX_IBO_3_UNK27));
if (img->bo) {
OUT_RELOCW(ring, img->bo, img->offset,
OUT_RELOC(ring, img->bo, img->offset,
(uint64_t)A6XX_IBO_5_DEPTH(img->depth) << 32, 0);
} else {
OUT_RING(ring, 0x00000000);
@ -272,7 +272,7 @@ static void emit_image_ssbo(struct fd_ringbuffer *ring, struct fd6_image *img)
if (ubwc_enabled) {
struct fdl_slice *ubwc_slice = &rsc->layout.ubwc_slices[img->level];
OUT_RELOCW(ring, rsc->bo, img->ubwc_offset, 0, 0);
OUT_RELOC(ring, rsc->bo, img->ubwc_offset, 0, 0);
OUT_RING(ring, A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
OUT_RING(ring, A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_slice->pitch));
} else {

24
src/gallium/drivers/freedreno/a6xx/fd6_query.c
View File

@ -68,7 +68,7 @@ occlusion_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
OUT_RELOCW(ring, query_sample(aq, start));
OUT_RELOC(ring, query_sample(aq, start));
fd6_event_write(batch, ring, ZPASS_DONE, false);
@ -81,7 +81,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch)
struct fd_ringbuffer *ring = batch->draw;
OUT_PKT7(ring, CP_MEM_WRITE, 4);
OUT_RELOCW(ring, query_sample(aq, stop));
OUT_RELOC(ring, query_sample(aq, stop));
OUT_RING(ring, 0xffffffff);
OUT_RING(ring, 0xffffffff);
@ -91,7 +91,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
OUT_RELOCW(ring, query_sample(aq, stop));
OUT_RELOC(ring, query_sample(aq, stop));
fd6_event_write(batch, ring, ZPASS_DONE, false);
@ -106,7 +106,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
CP_MEM_TO_MEM_0_NEG_C);
OUT_RELOCW(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* srcA */
OUT_RELOC(ring, query_sample(aq, stop)); /* srcB */
OUT_RELOC(ring, query_sample(aq, start)); /* srcC */
@ -166,7 +166,7 @@ timestamp_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS) |
CP_EVENT_WRITE_0_TIMESTAMP);
OUT_RELOCW(ring, query_sample(aq, start));
OUT_RELOC(ring, query_sample(aq, start));
OUT_RING(ring, 0x00000000);
fd_reset_wfi(batch);
@ -180,7 +180,7 @@ time_elapsed_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS) |
CP_EVENT_WRITE_0_TIMESTAMP);
OUT_RELOCW(ring, query_sample(aq, stop));
OUT_RELOC(ring, query_sample(aq, stop));
OUT_RING(ring, 0x00000000);
fd_reset_wfi(batch);
@ -190,7 +190,7 @@ time_elapsed_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
CP_MEM_TO_MEM_0_NEG_C);
OUT_RELOCW(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* dst */
OUT_RELOC(ring, query_sample(aq, result)); /* srcA */
OUT_RELOC(ring, query_sample(aq, stop)); /* srcB */
OUT_RELOC(ring, query_sample(aq, start)); /* srcC */
@ -209,7 +209,7 @@ record_timestamp(struct fd_ringbuffer *ring, struct fd_bo *bo, unsigned offset)
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS) |
CP_EVENT_WRITE_0_TIMESTAMP);
OUT_RELOCW(ring, bo, offset, 0, 0);
OUT_RELOC(ring, bo, offset, 0, 0);
OUT_RING(ring, 0x00000000);
}
@ -274,7 +274,7 @@ struct PACKED fd6_primitives_sample {
#define primitives_relocw(ring, aq, field) \
OUT_RELOCW(ring, fd_resource((aq)->prsc)->bo, offsetof(struct fd6_primitives_sample, field), 0, 0);
OUT_RELOC(ring, fd_resource((aq)->prsc)->bo, offsetof(struct fd6_primitives_sample, field), 0, 0);
#define primitives_reloc(ring, aq, field) \
OUT_RELOC(ring, fd_resource((aq)->prsc)->bo, offsetof(struct fd6_primitives_sample, field), 0, 0);
@ -499,7 +499,7 @@ perfcntr_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_64B |
CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
OUT_RELOCW(ring, query_sample_idx(aq, i, start));
OUT_RELOC(ring, query_sample_idx(aq, i, start));
}
}
@ -527,7 +527,7 @@ perfcntr_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_64B |
CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
OUT_RELOCW(ring, query_sample_idx(aq, i, stop));
OUT_RELOC(ring, query_sample_idx(aq, i, stop));
}
/* and compute the result: */
@ -536,7 +536,7 @@ perfcntr_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
CP_MEM_TO_MEM_0_NEG_C);
OUT_RELOCW(ring, query_sample_idx(aq, i, result)); /* dst */
OUT_RELOC(ring, query_sample_idx(aq, i, result)); /* dst */
OUT_RELOC(ring, query_sample_idx(aq, i, result)); /* srcA */
OUT_RELOC(ring, query_sample_idx(aq, i, stop)); /* srcB */
OUT_RELOC(ring, query_sample_idx(aq, i, start)); /* srcC */

2
src/gallium/drivers/freedreno/freedreno_query_hw.c
View File

@ -373,7 +373,7 @@ fd_hw_query_prepare_tile(struct fd_batch *batch, uint32_t n,
fd_wfi(batch, ring);
OUT_PKT0 (ring, HW_QUERY_BASE_REG, 1);
OUT_RELOCW(ring, fd_resource(batch->query_buf)->bo, offset, 0, 0);
OUT_RELOC(ring, fd_resource(batch->query_buf)->bo, offset, 0, 0);
}
void