i965/nir/vec4: Implement non-equality ops on vectors
Adds NIR ALU operations: * nir_op_bany_fnequal2 * nir_op_bany_inequal2 * nir_op_bany_fnequal3 * nir_op_bany_inequal3 * nir_op_bany_fnequal4 * nir_op_bany_inequal4 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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@ -955,6 +955,40 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
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break;
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}
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case nir_op_bany_fnequal2:
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case nir_op_bany_inequal2:
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case nir_op_bany_fnequal3:
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case nir_op_bany_inequal3:
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case nir_op_bany_fnequal4:
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case nir_op_bany_inequal4: {
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dst_reg tmp = dst_reg(this, glsl_type::bool_type);
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switch (instr->op) {
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case nir_op_bany_fnequal2:
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case nir_op_bany_inequal2:
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tmp.writemask = WRITEMASK_XY;
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break;
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case nir_op_bany_fnequal3:
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case nir_op_bany_inequal3:
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tmp.writemask = WRITEMASK_XYZ;
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break;
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case nir_op_bany_fnequal4:
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case nir_op_bany_inequal4:
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tmp.writemask = WRITEMASK_XYZW;
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break;
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default:
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unreachable("not reached");
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}
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emit(CMP(tmp, op[0], op[1],
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brw_conditional_for_nir_comparison(instr->op)));
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emit(MOV(dst, src_reg(0)));
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inst = emit(MOV(dst, src_reg(~0)));
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inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
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break;
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}
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default:
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unreachable("Unimplemented ALU operation");
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}
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