freedreno/a6xx: Add support for polygon fill mode (as long as front==back).
Unlike a4xx, we don't seem to have separate back vs front fields any more. Still, this improves desktop GL conformance (and one of the traces in traces-db). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
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50e20cb036
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@ -40,10 +40,8 @@ traces:
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checksum: 86d678c70b8adf27095ace1a6bbfe2d2
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checksum: 86d678c70b8adf27095ace1a6bbfe2d2
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- path: gputest/plot3d.trace
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- path: gputest/plot3d.trace
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expectations:
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expectations:
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# Actually incorrect rendering, it's supposed to be a mesh but
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# we're not doing polygon modes apparently.
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- device: freedreno-a630
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- device: freedreno-a630
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checksum: 8ec42780bfd9df16c49d876aa2f4cb8a
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checksum: 67a9eb692e694b11107860bbcd47d493
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# Note: Requires GL4 for tess.
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# Note: Requires GL4 for tess.
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- path: gputest/tessmark.trace
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- path: gputest/tessmark.trace
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expectations:
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expectations:
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@ -1194,9 +1194,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
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WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
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WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
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WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
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WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
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WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
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WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
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WRITE(REG_A6XX_PC_POLYGON_MODE, POLYMODE6_TRIANGLES);
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WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
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WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
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WRITE(REG_A6XX_VPC_POLYGON_MODE, POLYMODE6_TRIANGLES);
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WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
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WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
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/* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
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/* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
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* but this seems to kill texture gather offsets.
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* but this seems to kill texture gather offsets.
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@ -39,7 +39,7 @@ struct fd_ringbuffer *
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__fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
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__fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
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const struct pipe_rasterizer_state *cso, bool primitive_restart)
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const struct pipe_rasterizer_state *cso, bool primitive_restart)
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{
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{
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struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 14 * 4);
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struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
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float psize_min, psize_max;
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float psize_min, psize_max;
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if (cso->point_size_per_vertex) {
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if (cso->point_size_per_vertex) {
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@ -94,6 +94,22 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
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.primitive_restart = primitive_restart,
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.primitive_restart = primitive_restart,
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));
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));
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enum a6xx_polygon_mode mode = POLYMODE6_TRIANGLES;
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switch (cso->fill_front) {
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case PIPE_POLYGON_MODE_POINT:
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mode = POLYMODE6_POINTS;
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break;
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case PIPE_POLYGON_MODE_LINE:
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mode = POLYMODE6_LINES;
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break;
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default:
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assert(cso->fill_front == PIPE_POLYGON_MODE_FILL);
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break;
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}
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OUT_REG(ring, A6XX_VPC_POLYGON_MODE(.mode = mode));
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OUT_REG(ring, A6XX_PC_POLYGON_MODE(.mode = mode));
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return ring;
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return ring;
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}
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}
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