freedreno: update a2xx registers
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
This commit is contained in:
Jonathan Marek
Rob Clark
parent
fb78a6cb72
commit
501c6e70d4
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@ -8,17 +8,10 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-21 18:21:34)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-21 18:21:34)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 141895 bytes, from 2018-12-21 18:21:34)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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- ./rnndb/adreno/a2xx.xml ( 79608 bytes, from 2018-12-21 03:07:09)
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- ./rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-09-02 13:35:19)
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- ./rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-09-07 18:12:21)
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- ./rnndb/adreno/adreno_pm4.xml ( 42626 bytes, from 2018-09-17 18:20:14)
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Copyright (C) 2013-2018 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -210,6 +203,669 @@ enum a2xx_rb_blend_opcode {
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BLEND2_DST_PLUS_SRC_BIAS = 5,
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};
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enum a2xx_su_perfcnt_select {
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PERF_PAPC_PASX_REQ = 0,
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PERF_PAPC_PASX_FIRST_VECTOR = 2,
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PERF_PAPC_PASX_SECOND_VECTOR = 3,
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PERF_PAPC_PASX_FIRST_DEAD = 4,
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PERF_PAPC_PASX_SECOND_DEAD = 5,
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PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
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PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
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PERF_PAPC_PA_INPUT_PRIM = 8,
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PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
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PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
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PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
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PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
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PERF_PAPC_CLPR_CULL_PRIM = 13,
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PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
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PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
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PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
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PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
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PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
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PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
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PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
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PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
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PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
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PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
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PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
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PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
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PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
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PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
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PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
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PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
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PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
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PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
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PERF_PAPC_CLSM_NULL_PRIM = 36,
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PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
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PERF_PAPC_CLSM_CLIP_PRIM = 38,
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PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
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PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
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PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
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PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
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PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
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PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
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PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
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PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
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PERF_PAPC_SU_INPUT_PRIM = 47,
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PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
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PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
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PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
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PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
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PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
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PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
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PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
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PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
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PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
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PERF_PAPC_SU_OUTPUT_PRIM = 57,
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PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
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PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
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PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
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PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
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PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
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PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
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PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
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PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
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PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
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PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
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PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
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PERF_PAPC_PASX_REQ_IDLE = 69,
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PERF_PAPC_PASX_REQ_BUSY = 70,
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PERF_PAPC_PASX_REQ_STALLED = 71,
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PERF_PAPC_PASX_REC_IDLE = 72,
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PERF_PAPC_PASX_REC_BUSY = 73,
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PERF_PAPC_PASX_REC_STARVED_SX = 74,
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PERF_PAPC_PASX_REC_STALLED = 75,
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PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
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PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
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PERF_PAPC_CCGSM_IDLE = 78,
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PERF_PAPC_CCGSM_BUSY = 79,
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PERF_PAPC_CCGSM_STALLED = 80,
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PERF_PAPC_CLPRIM_IDLE = 81,
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PERF_PAPC_CLPRIM_BUSY = 82,
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PERF_PAPC_CLPRIM_STALLED = 83,
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PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
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PERF_PAPC_CLIPSM_IDLE = 85,
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PERF_PAPC_CLIPSM_BUSY = 86,
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PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
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PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
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PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
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PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
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PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
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PERF_PAPC_CLIPGA_IDLE = 92,
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PERF_PAPC_CLIPGA_BUSY = 93,
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PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
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PERF_PAPC_CLIPGA_STALLED = 95,
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PERF_PAPC_CLIP_IDLE = 96,
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PERF_PAPC_CLIP_BUSY = 97,
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PERF_PAPC_SU_IDLE = 98,
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PERF_PAPC_SU_BUSY = 99,
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PERF_PAPC_SU_STARVED_CLIP = 100,
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PERF_PAPC_SU_STALLED_SC = 101,
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PERF_PAPC_SU_FACENESS_CULL = 102,
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};
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enum a2xx_sc_perfcnt_select {
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SC_SR_WINDOW_VALID = 0,
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SC_CW_WINDOW_VALID = 1,
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SC_QM_WINDOW_VALID = 2,
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SC_FW_WINDOW_VALID = 3,
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SC_EZ_WINDOW_VALID = 4,
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SC_IT_WINDOW_VALID = 5,
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SC_STARVED_BY_PA = 6,
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SC_STALLED_BY_RB_TILE = 7,
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SC_STALLED_BY_RB_SAMP = 8,
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SC_STARVED_BY_RB_EZ = 9,
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SC_STALLED_BY_SAMPLE_FF = 10,
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SC_STALLED_BY_SQ = 11,
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SC_STALLED_BY_SP = 12,
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SC_TOTAL_NO_PRIMS = 13,
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SC_NON_EMPTY_PRIMS = 14,
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SC_NO_TILES_PASSING_QM = 15,
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SC_NO_PIXELS_PRE_EZ = 16,
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SC_NO_PIXELS_POST_EZ = 17,
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};
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enum a2xx_vgt_perfcount_select {
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VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
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VGT_SQ_SEND = 1,
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VGT_SQ_STALLED = 2,
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VGT_SQ_STARVED_BUSY = 3,
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VGT_SQ_STARVED_IDLE = 4,
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VGT_SQ_STATIC = 5,
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VGT_PA_EVENT_WINDOW_ACTIVE = 6,
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VGT_PA_CLIP_V_SEND = 7,
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VGT_PA_CLIP_V_STALLED = 8,
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VGT_PA_CLIP_V_STARVED_BUSY = 9,
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VGT_PA_CLIP_V_STARVED_IDLE = 10,
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VGT_PA_CLIP_V_STATIC = 11,
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VGT_PA_CLIP_P_SEND = 12,
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VGT_PA_CLIP_P_STALLED = 13,
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VGT_PA_CLIP_P_STARVED_BUSY = 14,
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VGT_PA_CLIP_P_STARVED_IDLE = 15,
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VGT_PA_CLIP_P_STATIC = 16,
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VGT_PA_CLIP_S_SEND = 17,
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VGT_PA_CLIP_S_STALLED = 18,
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VGT_PA_CLIP_S_STARVED_BUSY = 19,
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VGT_PA_CLIP_S_STARVED_IDLE = 20,
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VGT_PA_CLIP_S_STATIC = 21,
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RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
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RBIU_IMMED_DATA_FIFO_STARVED = 23,
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RBIU_IMMED_DATA_FIFO_STALLED = 24,
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RBIU_DMA_REQUEST_FIFO_STARVED = 25,
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RBIU_DMA_REQUEST_FIFO_STALLED = 26,
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RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
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RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
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BIN_PRIM_NEAR_CULL = 29,
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BIN_PRIM_ZERO_CULL = 30,
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BIN_PRIM_FAR_CULL = 31,
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BIN_PRIM_BIN_CULL = 32,
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BIN_PRIM_FACE_CULL = 33,
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SPARE34 = 34,
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SPARE35 = 35,
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SPARE36 = 36,
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SPARE37 = 37,
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SPARE38 = 38,
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SPARE39 = 39,
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TE_SU_IN_VALID = 40,
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TE_SU_IN_READ = 41,
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TE_SU_IN_PRIM = 42,
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TE_SU_IN_EOP = 43,
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TE_SU_IN_NULL_PRIM = 44,
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TE_WK_IN_VALID = 45,
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TE_WK_IN_READ = 46,
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TE_OUT_PRIM_VALID = 47,
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TE_OUT_PRIM_READ = 48,
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};
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enum a2xx_tcr_perfcount_select {
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DGMMPD_IPMUX0_STALL = 0,
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DGMMPD_IPMUX_ALL_STALL = 4,
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OPMUX0_L2_WRITES = 5,
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};
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enum a2xx_tp_perfcount_select {
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POINT_QUADS = 0,
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BILIN_QUADS = 1,
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ANISO_QUADS = 2,
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MIP_QUADS = 3,
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VOL_QUADS = 4,
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MIP_VOL_QUADS = 5,
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MIP_ANISO_QUADS = 6,
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VOL_ANISO_QUADS = 7,
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ANISO_2_1_QUADS = 8,
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ANISO_4_1_QUADS = 9,
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ANISO_6_1_QUADS = 10,
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ANISO_8_1_QUADS = 11,
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ANISO_10_1_QUADS = 12,
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ANISO_12_1_QUADS = 13,
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ANISO_14_1_QUADS = 14,
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ANISO_16_1_QUADS = 15,
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MIP_VOL_ANISO_QUADS = 16,
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ALIGN_2_QUADS = 17,
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ALIGN_4_QUADS = 18,
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PIX_0_QUAD = 19,
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PIX_1_QUAD = 20,
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PIX_2_QUAD = 21,
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PIX_3_QUAD = 22,
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PIX_4_QUAD = 23,
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TP_MIPMAP_LOD0 = 24,
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TP_MIPMAP_LOD1 = 25,
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TP_MIPMAP_LOD2 = 26,
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TP_MIPMAP_LOD3 = 27,
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TP_MIPMAP_LOD4 = 28,
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TP_MIPMAP_LOD5 = 29,
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TP_MIPMAP_LOD6 = 30,
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TP_MIPMAP_LOD7 = 31,
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TP_MIPMAP_LOD8 = 32,
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TP_MIPMAP_LOD9 = 33,
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TP_MIPMAP_LOD10 = 34,
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TP_MIPMAP_LOD11 = 35,
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TP_MIPMAP_LOD12 = 36,
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TP_MIPMAP_LOD13 = 37,
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TP_MIPMAP_LOD14 = 38,
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};
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enum a2xx_tcm_perfcount_select {
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QUAD0_RD_LAT_FIFO_EMPTY = 0,
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QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
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QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
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QUAD0_RD_LAT_FIFO_FULL = 5,
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QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
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READ_STARVED_QUAD0 = 28,
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READ_STARVED = 32,
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READ_STALLED_QUAD0 = 33,
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READ_STALLED = 37,
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VALID_READ_QUAD0 = 38,
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TC_TP_STARVED_QUAD0 = 42,
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TC_TP_STARVED = 46,
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};
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enum a2xx_tcf_perfcount_select {
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VALID_CYCLES = 0,
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SINGLE_PHASES = 1,
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ANISO_PHASES = 2,
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MIP_PHASES = 3,
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VOL_PHASES = 4,
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MIP_VOL_PHASES = 5,
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MIP_ANISO_PHASES = 6,
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VOL_ANISO_PHASES = 7,
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ANISO_2_1_PHASES = 8,
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ANISO_4_1_PHASES = 9,
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ANISO_6_1_PHASES = 10,
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ANISO_8_1_PHASES = 11,
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ANISO_10_1_PHASES = 12,
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ANISO_12_1_PHASES = 13,
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ANISO_14_1_PHASES = 14,
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ANISO_16_1_PHASES = 15,
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MIP_VOL_ANISO_PHASES = 16,
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ALIGN_2_PHASES = 17,
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ALIGN_4_PHASES = 18,
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TPC_BUSY = 19,
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TPC_STALLED = 20,
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TPC_STARVED = 21,
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TPC_WORKING = 22,
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TPC_WALKER_BUSY = 23,
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TPC_WALKER_STALLED = 24,
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TPC_WALKER_WORKING = 25,
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TPC_ALIGNER_BUSY = 26,
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TPC_ALIGNER_STALLED = 27,
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TPC_ALIGNER_STALLED_BY_BLEND = 28,
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TPC_ALIGNER_STALLED_BY_CACHE = 29,
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TPC_ALIGNER_WORKING = 30,
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TPC_BLEND_BUSY = 31,
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TPC_BLEND_SYNC = 32,
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TPC_BLEND_STARVED = 33,
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TPC_BLEND_WORKING = 34,
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OPCODE_0x00 = 35,
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OPCODE_0x01 = 36,
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OPCODE_0x04 = 37,
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OPCODE_0x10 = 38,
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OPCODE_0x11 = 39,
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OPCODE_0x12 = 40,
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OPCODE_0x13 = 41,
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OPCODE_0x18 = 42,
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OPCODE_0x19 = 43,
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OPCODE_0x1A = 44,
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OPCODE_OTHER = 45,
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IN_FIFO_0_EMPTY = 56,
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IN_FIFO_0_LT_HALF_FULL = 57,
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IN_FIFO_0_HALF_FULL = 58,
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IN_FIFO_0_FULL = 59,
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IN_FIFO_TPC_EMPTY = 72,
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IN_FIFO_TPC_LT_HALF_FULL = 73,
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IN_FIFO_TPC_HALF_FULL = 74,
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IN_FIFO_TPC_FULL = 75,
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TPC_TC_XFC = 76,
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TPC_TC_STATE = 77,
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TC_STALL = 78,
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QUAD0_TAPS = 79,
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QUADS = 83,
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TCA_SYNC_STALL = 84,
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TAG_STALL = 85,
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TCB_SYNC_STALL = 88,
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TCA_VALID = 89,
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PROBES_VALID = 90,
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MISS_STALL = 91,
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FETCH_FIFO_STALL = 92,
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TCO_STALL = 93,
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ANY_STALL = 94,
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TAG_MISSES = 95,
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TAG_HITS = 96,
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SUB_TAG_MISSES = 97,
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SET0_INVALIDATES = 98,
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SET1_INVALIDATES = 99,
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SET2_INVALIDATES = 100,
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||||
SET3_INVALIDATES = 101,
|
||||
SET0_TAG_MISSES = 102,
|
||||
SET1_TAG_MISSES = 103,
|
||||
SET2_TAG_MISSES = 104,
|
||||
SET3_TAG_MISSES = 105,
|
||||
SET0_TAG_HITS = 106,
|
||||
SET1_TAG_HITS = 107,
|
||||
SET2_TAG_HITS = 108,
|
||||
SET3_TAG_HITS = 109,
|
||||
SET0_SUB_TAG_MISSES = 110,
|
||||
SET1_SUB_TAG_MISSES = 111,
|
||||
SET2_SUB_TAG_MISSES = 112,
|
||||
SET3_SUB_TAG_MISSES = 113,
|
||||
SET0_EVICT1 = 114,
|
||||
SET0_EVICT2 = 115,
|
||||
SET0_EVICT3 = 116,
|
||||
SET0_EVICT4 = 117,
|
||||
SET0_EVICT5 = 118,
|
||||
SET0_EVICT6 = 119,
|
||||
SET0_EVICT7 = 120,
|
||||
SET0_EVICT8 = 121,
|
||||
SET1_EVICT1 = 130,
|
||||
SET1_EVICT2 = 131,
|
||||
SET1_EVICT3 = 132,
|
||||
SET1_EVICT4 = 133,
|
||||
SET1_EVICT5 = 134,
|
||||
SET1_EVICT6 = 135,
|
||||
SET1_EVICT7 = 136,
|
||||
SET1_EVICT8 = 137,
|
||||
SET2_EVICT1 = 146,
|
||||
SET2_EVICT2 = 147,
|
||||
SET2_EVICT3 = 148,
|
||||
SET2_EVICT4 = 149,
|
||||
SET2_EVICT5 = 150,
|
||||
SET2_EVICT6 = 151,
|
||||
SET2_EVICT7 = 152,
|
||||
SET2_EVICT8 = 153,
|
||||
SET3_EVICT1 = 162,
|
||||
SET3_EVICT2 = 163,
|
||||
SET3_EVICT3 = 164,
|
||||
SET3_EVICT4 = 165,
|
||||
SET3_EVICT5 = 166,
|
||||
SET3_EVICT6 = 167,
|
||||
SET3_EVICT7 = 168,
|
||||
SET3_EVICT8 = 169,
|
||||
FF_EMPTY = 178,
|
||||
FF_LT_HALF_FULL = 179,
|
||||
FF_HALF_FULL = 180,
|
||||
FF_FULL = 181,
|
||||
FF_XFC = 182,
|
||||
FF_STALLED = 183,
|
||||
FG_MASKS = 184,
|
||||
FG_LEFT_MASKS = 185,
|
||||
FG_LEFT_MASK_STALLED = 186,
|
||||
FG_LEFT_NOT_DONE_STALL = 187,
|
||||
FG_LEFT_FG_STALL = 188,
|
||||
FG_LEFT_SECTORS = 189,
|
||||
FG0_REQUESTS = 195,
|
||||
FG0_STALLED = 196,
|
||||
MEM_REQ512 = 199,
|
||||
MEM_REQ_SENT = 200,
|
||||
MEM_LOCAL_READ_REQ = 202,
|
||||
TC0_MH_STALLED = 203,
|
||||
};
|
||||
|
||||
enum a2xx_sq_perfcnt_select {
|
||||
SQ_PIXEL_VECTORS_SUB = 0,
|
||||
SQ_VERTEX_VECTORS_SUB = 1,
|
||||
SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
|
||||
SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
|
||||
SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
|
||||
SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
|
||||
SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
|
||||
SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
|
||||
SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
|
||||
SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
|
||||
SQ_EXPORT_CYCLES = 10,
|
||||
SQ_ALU_CST_WRITTEN = 11,
|
||||
SQ_TEX_CST_WRITTEN = 12,
|
||||
SQ_ALU_CST_STALL = 13,
|
||||
SQ_ALU_TEX_STALL = 14,
|
||||
SQ_INST_WRITTEN = 15,
|
||||
SQ_BOOLEAN_WRITTEN = 16,
|
||||
SQ_LOOPS_WRITTEN = 17,
|
||||
SQ_PIXEL_SWAP_IN = 18,
|
||||
SQ_PIXEL_SWAP_OUT = 19,
|
||||
SQ_VERTEX_SWAP_IN = 20,
|
||||
SQ_VERTEX_SWAP_OUT = 21,
|
||||
SQ_ALU_VTX_INST_ISSUED = 22,
|
||||
SQ_TEX_VTX_INST_ISSUED = 23,
|
||||
SQ_VC_VTX_INST_ISSUED = 24,
|
||||
SQ_CF_VTX_INST_ISSUED = 25,
|
||||
SQ_ALU_PIX_INST_ISSUED = 26,
|
||||
SQ_TEX_PIX_INST_ISSUED = 27,
|
||||
SQ_VC_PIX_INST_ISSUED = 28,
|
||||
SQ_CF_PIX_INST_ISSUED = 29,
|
||||
SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
|
||||
SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
|
||||
SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
|
||||
SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
|
||||
SQ_ALU_NOPS = 34,
|
||||
SQ_PRED_SKIP = 35,
|
||||
SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
|
||||
SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
|
||||
SQ_SYNC_TEX_STALL_VTX = 38,
|
||||
SQ_SYNC_VC_STALL_VTX = 39,
|
||||
SQ_CONSTANTS_USED_SIMD0 = 40,
|
||||
SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
|
||||
SQ_GPR_STALL_VTX = 42,
|
||||
SQ_GPR_STALL_PIX = 43,
|
||||
SQ_VTX_RS_STALL = 44,
|
||||
SQ_PIX_RS_STALL = 45,
|
||||
SQ_SX_PC_FULL = 46,
|
||||
SQ_SX_EXP_BUFF_FULL = 47,
|
||||
SQ_SX_POS_BUFF_FULL = 48,
|
||||
SQ_INTERP_QUADS = 49,
|
||||
SQ_INTERP_ACTIVE = 50,
|
||||
SQ_IN_PIXEL_STALL = 51,
|
||||
SQ_IN_VTX_STALL = 52,
|
||||
SQ_VTX_CNT = 53,
|
||||
SQ_VTX_VECTOR2 = 54,
|
||||
SQ_VTX_VECTOR3 = 55,
|
||||
SQ_VTX_VECTOR4 = 56,
|
||||
SQ_PIXEL_VECTOR1 = 57,
|
||||
SQ_PIXEL_VECTOR23 = 58,
|
||||
SQ_PIXEL_VECTOR4 = 59,
|
||||
SQ_CONSTANTS_USED_SIMD1 = 60,
|
||||
SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
|
||||
SQ_SX_MEM_EXP_FULL = 62,
|
||||
SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
|
||||
SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
|
||||
SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
|
||||
SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
|
||||
SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
|
||||
SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
|
||||
SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
|
||||
SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
|
||||
SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
|
||||
SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
|
||||
SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
|
||||
SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
|
||||
SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
|
||||
SQ_PERFCOUNT_VTX_POP_THREAD = 76,
|
||||
SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
|
||||
SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
|
||||
SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
|
||||
SQ_PERFCOUNT_PIX_POP_THREAD = 80,
|
||||
SQ_SYNC_TEX_STALL_PIX = 81,
|
||||
SQ_SYNC_VC_STALL_PIX = 82,
|
||||
SQ_CONSTANTS_USED_SIMD2 = 83,
|
||||
SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
|
||||
SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
|
||||
SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
|
||||
SQ_ALU0_FIFO_FULL_SIMD0 = 87,
|
||||
SQ_ALU1_FIFO_FULL_SIMD0 = 88,
|
||||
SQ_ALU0_FIFO_FULL_SIMD1 = 89,
|
||||
SQ_ALU1_FIFO_FULL_SIMD1 = 90,
|
||||
SQ_ALU0_FIFO_FULL_SIMD2 = 91,
|
||||
SQ_ALU1_FIFO_FULL_SIMD2 = 92,
|
||||
SQ_ALU0_FIFO_FULL_SIMD3 = 93,
|
||||
SQ_ALU1_FIFO_FULL_SIMD3 = 94,
|
||||
VC_PERF_STATIC = 95,
|
||||
VC_PERF_STALLED = 96,
|
||||
VC_PERF_STARVED = 97,
|
||||
VC_PERF_SEND = 98,
|
||||
VC_PERF_ACTUAL_STARVED = 99,
|
||||
PIXEL_THREAD_0_ACTIVE = 100,
|
||||
VERTEX_THREAD_0_ACTIVE = 101,
|
||||
PIXEL_THREAD_0_NUMBER = 102,
|
||||
VERTEX_THREAD_0_NUMBER = 103,
|
||||
VERTEX_EVENT_NUMBER = 104,
|
||||
PIXEL_EVENT_NUMBER = 105,
|
||||
PTRBUFF_EF_PUSH = 106,
|
||||
PTRBUFF_EF_POP_EVENT = 107,
|
||||
PTRBUFF_EF_POP_NEW_VTX = 108,
|
||||
PTRBUFF_EF_POP_DEALLOC = 109,
|
||||
PTRBUFF_EF_POP_PVECTOR = 110,
|
||||
PTRBUFF_EF_POP_PVECTOR_X = 111,
|
||||
PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
|
||||
PTRBUFF_PB_DEALLOC = 113,
|
||||
PTRBUFF_PI_STATE_PPB_POP = 114,
|
||||
PTRBUFF_PI_RTR = 115,
|
||||
PTRBUFF_PI_READ_EN = 116,
|
||||
PTRBUFF_PI_BUFF_SWAP = 117,
|
||||
PTRBUFF_SQ_FREE_BUFF = 118,
|
||||
PTRBUFF_SQ_DEC = 119,
|
||||
PTRBUFF_SC_VALID_CNTL_EVENT = 120,
|
||||
PTRBUFF_SC_VALID_IJ_XFER = 121,
|
||||
PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
|
||||
PTRBUFF_QUAL_NEW_VECTOR = 123,
|
||||
PTRBUFF_QUAL_EVENT = 124,
|
||||
PTRBUFF_END_BUFFER = 125,
|
||||
PTRBUFF_FILL_QUAD = 126,
|
||||
VERTS_WRITTEN_SPI = 127,
|
||||
TP_FETCH_INSTR_EXEC = 128,
|
||||
TP_FETCH_INSTR_REQ = 129,
|
||||
TP_DATA_RETURN = 130,
|
||||
SPI_WRITE_CYCLES_SP = 131,
|
||||
SPI_WRITES_SP = 132,
|
||||
SP_ALU_INSTR_EXEC = 133,
|
||||
SP_CONST_ADDR_TO_SQ = 134,
|
||||
SP_PRED_KILLS_TO_SQ = 135,
|
||||
SP_EXPORT_CYCLES_TO_SX = 136,
|
||||
SP_EXPORTS_TO_SX = 137,
|
||||
SQ_CYCLES_ELAPSED = 138,
|
||||
SQ_TCFS_OPT_ALLOC_EXEC = 139,
|
||||
SQ_TCFS_NO_OPT_ALLOC = 140,
|
||||
SQ_ALU0_NO_OPT_ALLOC = 141,
|
||||
SQ_ALU1_NO_OPT_ALLOC = 142,
|
||||
SQ_TCFS_ARB_XFC_CNT = 143,
|
||||
SQ_ALU0_ARB_XFC_CNT = 144,
|
||||
SQ_ALU1_ARB_XFC_CNT = 145,
|
||||
SQ_TCFS_CFS_UPDATE_CNT = 146,
|
||||
SQ_ALU0_CFS_UPDATE_CNT = 147,
|
||||
SQ_ALU1_CFS_UPDATE_CNT = 148,
|
||||
SQ_VTX_PUSH_THREAD_CNT = 149,
|
||||
SQ_VTX_POP_THREAD_CNT = 150,
|
||||
SQ_PIX_PUSH_THREAD_CNT = 151,
|
||||
SQ_PIX_POP_THREAD_CNT = 152,
|
||||
SQ_PIX_TOTAL = 153,
|
||||
SQ_PIX_KILLED = 154,
|
||||
};
|
||||
|
||||
enum a2xx_sx_perfcnt_select {
|
||||
SX_EXPORT_VECTORS = 0,
|
||||
SX_DUMMY_QUADS = 1,
|
||||
SX_ALPHA_FAIL = 2,
|
||||
SX_RB_QUAD_BUSY = 3,
|
||||
SX_RB_COLOR_BUSY = 4,
|
||||
SX_RB_QUAD_STALL = 5,
|
||||
SX_RB_COLOR_STALL = 6,
|
||||
};
|
||||
|
||||
enum a2xx_rbbm_perfcount1_sel {
|
||||
RBBM1_COUNT = 0,
|
||||
RBBM1_NRT_BUSY = 1,
|
||||
RBBM1_RB_BUSY = 2,
|
||||
RBBM1_SQ_CNTX0_BUSY = 3,
|
||||
RBBM1_SQ_CNTX17_BUSY = 4,
|
||||
RBBM1_VGT_BUSY = 5,
|
||||
RBBM1_VGT_NODMA_BUSY = 6,
|
||||
RBBM1_PA_BUSY = 7,
|
||||
RBBM1_SC_CNTX_BUSY = 8,
|
||||
RBBM1_TPC_BUSY = 9,
|
||||
RBBM1_TC_BUSY = 10,
|
||||
RBBM1_SX_BUSY = 11,
|
||||
RBBM1_CP_COHER_BUSY = 12,
|
||||
RBBM1_CP_NRT_BUSY = 13,
|
||||
RBBM1_GFX_IDLE_STALL = 14,
|
||||
RBBM1_INTERRUPT = 15,
|
||||
};
|
||||
|
||||
enum a2xx_cp_perfcount_sel {
|
||||
ALWAYS_COUNT = 0,
|
||||
TRANS_FIFO_FULL = 1,
|
||||
TRANS_FIFO_AF = 2,
|
||||
RCIU_PFPTRANS_WAIT = 3,
|
||||
RCIU_NRTTRANS_WAIT = 6,
|
||||
CSF_NRT_READ_WAIT = 8,
|
||||
CSF_I1_FIFO_FULL = 9,
|
||||
CSF_I2_FIFO_FULL = 10,
|
||||
CSF_ST_FIFO_FULL = 11,
|
||||
CSF_RING_ROQ_FULL = 13,
|
||||
CSF_I1_ROQ_FULL = 14,
|
||||
CSF_I2_ROQ_FULL = 15,
|
||||
CSF_ST_ROQ_FULL = 16,
|
||||
MIU_TAG_MEM_FULL = 18,
|
||||
MIU_WRITECLEAN = 19,
|
||||
MIU_NRT_WRITE_STALLED = 22,
|
||||
MIU_NRT_READ_STALLED = 23,
|
||||
ME_WRITE_CONFIRM_FIFO_FULL = 24,
|
||||
ME_VS_DEALLOC_FIFO_FULL = 25,
|
||||
ME_PS_DEALLOC_FIFO_FULL = 26,
|
||||
ME_REGS_VS_EVENT_FIFO_FULL = 27,
|
||||
ME_REGS_PS_EVENT_FIFO_FULL = 28,
|
||||
ME_REGS_CF_EVENT_FIFO_FULL = 29,
|
||||
ME_MICRO_RB_STARVED = 30,
|
||||
ME_MICRO_I1_STARVED = 31,
|
||||
ME_MICRO_I2_STARVED = 32,
|
||||
ME_MICRO_ST_STARVED = 33,
|
||||
RCIU_RBBM_DWORD_SENT = 40,
|
||||
ME_BUSY_CLOCKS = 41,
|
||||
ME_WAIT_CONTEXT_AVAIL = 42,
|
||||
PFP_TYPE0_PACKET = 43,
|
||||
PFP_TYPE3_PACKET = 44,
|
||||
CSF_RB_WPTR_NEQ_RPTR = 45,
|
||||
CSF_I1_SIZE_NEQ_ZERO = 46,
|
||||
CSF_I2_SIZE_NEQ_ZERO = 47,
|
||||
CSF_RBI1I2_FETCHING = 48,
|
||||
};
|
||||
|
||||
enum a2xx_rb_perfcnt_select {
|
||||
RBPERF_CNTX_BUSY = 0,
|
||||
RBPERF_CNTX_BUSY_MAX = 1,
|
||||
RBPERF_SX_QUAD_STARVED = 2,
|
||||
RBPERF_SX_QUAD_STARVED_MAX = 3,
|
||||
RBPERF_GA_GC_CH0_SYS_REQ = 4,
|
||||
RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
|
||||
RBPERF_GA_GC_CH1_SYS_REQ = 6,
|
||||
RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
|
||||
RBPERF_MH_STARVED = 8,
|
||||
RBPERF_MH_STARVED_MAX = 9,
|
||||
RBPERF_AZ_BC_COLOR_BUSY = 10,
|
||||
RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
|
||||
RBPERF_AZ_BC_Z_BUSY = 12,
|
||||
RBPERF_AZ_BC_Z_BUSY_MAX = 13,
|
||||
RBPERF_RB_SC_TILE_RTR_N = 14,
|
||||
RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
|
||||
RBPERF_RB_SC_SAMP_RTR_N = 16,
|
||||
RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
|
||||
RBPERF_RB_SX_QUAD_RTR_N = 18,
|
||||
RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
|
||||
RBPERF_RB_SX_COLOR_RTR_N = 20,
|
||||
RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
|
||||
RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
|
||||
RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
|
||||
RBPERF_ZXP_STALL = 24,
|
||||
RBPERF_ZXP_STALL_MAX = 25,
|
||||
RBPERF_EVENT_PENDING = 26,
|
||||
RBPERF_EVENT_PENDING_MAX = 27,
|
||||
RBPERF_RB_MH_VALID = 28,
|
||||
RBPERF_RB_MH_VALID_MAX = 29,
|
||||
RBPERF_SX_RB_QUAD_SEND = 30,
|
||||
RBPERF_SX_RB_COLOR_SEND = 31,
|
||||
RBPERF_SC_RB_TILE_SEND = 32,
|
||||
RBPERF_SC_RB_SAMPLE_SEND = 33,
|
||||
RBPERF_SX_RB_MEM_EXPORT = 34,
|
||||
RBPERF_SX_RB_QUAD_EVENT = 35,
|
||||
RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
|
||||
RBPERF_SC_RB_TILE_EVENT_ALL = 37,
|
||||
RBPERF_RB_SC_EZ_SEND = 38,
|
||||
RBPERF_RB_SX_INDEX_SEND = 39,
|
||||
RBPERF_GMEM_INTFO_RD = 40,
|
||||
RBPERF_GMEM_INTF1_RD = 41,
|
||||
RBPERF_GMEM_INTFO_WR = 42,
|
||||
RBPERF_GMEM_INTF1_WR = 43,
|
||||
RBPERF_RB_CP_CONTEXT_DONE = 44,
|
||||
RBPERF_RB_CP_CACHE_FLUSH = 45,
|
||||
RBPERF_ZPASS_DONE = 46,
|
||||
RBPERF_ZCMD_VALID = 47,
|
||||
RBPERF_CCMD_VALID = 48,
|
||||
RBPERF_ACCUM_GRANT = 49,
|
||||
RBPERF_ACCUM_C0_GRANT = 50,
|
||||
RBPERF_ACCUM_C1_GRANT = 51,
|
||||
RBPERF_ACCUM_FULL_BE_WR = 52,
|
||||
RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
|
||||
RBPERF_ACCUM_TIMEOUT_PULSE = 54,
|
||||
RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
|
||||
RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
|
||||
};
|
||||
|
||||
enum adreno_mmu_clnt_beh {
|
||||
BEH_NEVR = 0,
|
||||
BEH_TRAN_RNG = 1,
|
||||
|
|
@ -1863,6 +2519,232 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
|
|||
|
||||
#define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92
|
||||
|
||||
#define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93
|
||||
|
||||
#define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98
|
||||
|
||||
#define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99
|
||||
|
||||
#define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51
|
||||
|
||||
#define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53
|
||||
|
||||
#define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05
|
||||
|
||||
#define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08
|
||||
|
||||
#define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06
|
||||
|
||||
#define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09
|
||||
|
||||
#define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07
|
||||
|
||||
#define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a
|
||||
|
||||
#define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f
|
||||
|
||||
#define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20
|
||||
|
||||
#define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21
|
||||
|
||||
#define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22
|
||||
|
||||
#define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23
|
||||
|
||||
#define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24
|
||||
|
||||
#define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54
|
||||
|
||||
#define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57
|
||||
|
||||
#define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55
|
||||
|
||||
#define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58
|
||||
|
||||
#define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56
|
||||
|
||||
#define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a
|
||||
|
||||
#define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2
|
||||
|
||||
#define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3
|
||||
|
||||
#define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4
|
||||
|
||||
#define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8
|
||||
|
||||
#define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49
|
||||
|
||||
#define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
|
||||
|
||||
#define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445
|
||||
|
||||
#define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446
|
||||
|
||||
#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
|
||||
|
||||
#define REG_A2XX_SQ_TEX_0 0x00000000
|
||||
#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
|
||||
#define A2XX_SQ_TEX_0_TYPE__SHIFT 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue