lavapipe: accurately set image/ssbo access based on shader usage
Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15286>
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@ -43,6 +43,7 @@
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#include "util/u_prim_restart.h"
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#include "util/format/u_format_zs.h"
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#include "util/ptralloc.h"
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#include "tgsi/tgsi_from_mesa.h"
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#include "vk_cmd_enqueue_entrypoints.h"
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#include "vk_util.h"
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@ -127,6 +128,7 @@ struct rendering_state {
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struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
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struct cso_velems_state velem;
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struct lvp_access_info access[MESA_SHADER_STAGES];
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struct pipe_sampler_view *sv[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_SAMPLER_VIEWS];
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int num_sampler_views[PIPE_SHADER_TYPES];
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struct pipe_sampler_state ss[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
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@ -397,7 +399,7 @@ static void emit_state(struct rendering_state *state)
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if (state->sb_dirty[sh]) {
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state->pctx->set_shader_buffers(state->pctx, sh,
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0, state->num_shader_buffers[sh],
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state->sb[sh], (1 << state->num_shader_buffers[sh]) - 1);
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state->sb[sh], state->access[tgsi_processor_to_shader_stage(sh)].buffers_written);
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}
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}
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@ -450,6 +452,13 @@ static void handle_compute_pipeline(struct vk_cmd_queue_entry *cmd,
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if (!state->has_pcbuf[PIPE_SHADER_COMPUTE] && !pipeline->layout->stage[MESA_SHADER_COMPUTE].uniform_block_count)
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state->pcbuf_dirty[PIPE_SHADER_COMPUTE] = false;
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state->iv_dirty[MESA_SHADER_COMPUTE] |= state->num_shader_images[MESA_SHADER_COMPUTE] &&
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(state->access[MESA_SHADER_COMPUTE].images_read != pipeline->access[MESA_SHADER_COMPUTE].images_read ||
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state->access[MESA_SHADER_COMPUTE].images_written != pipeline->access[MESA_SHADER_COMPUTE].images_written);
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state->sb_dirty[MESA_SHADER_COMPUTE] |= state->num_shader_buffers[MESA_SHADER_COMPUTE] &&
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state->access[MESA_SHADER_COMPUTE].buffers_written != pipeline->access[MESA_SHADER_COMPUTE].buffers_written;
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memcpy(&state->access[MESA_SHADER_COMPUTE], &pipeline->access[MESA_SHADER_COMPUTE], sizeof(struct lvp_access_info));
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state->dispatch_info.block[0] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[0];
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state->dispatch_info.block[1] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[1];
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state->dispatch_info.block[2] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[2];
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@ -559,6 +568,14 @@ static void handle_graphics_pipeline(struct vk_cmd_queue_entry *cmd,
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unsigned fb_samples = 0;
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bool clip_halfz = state->rs_state.clip_halfz;
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for (enum pipe_shader_type sh = PIPE_SHADER_VERTEX; sh < PIPE_SHADER_COMPUTE; sh++) {
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state->iv_dirty[sh] |= state->num_shader_images[sh] &&
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(state->access[sh].images_read != pipeline->access[sh].images_read ||
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state->access[sh].images_written != pipeline->access[sh].images_written);
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state->sb_dirty[sh] |= state->num_shader_buffers[sh] && state->access[sh].buffers_written != pipeline->access[sh].buffers_written;
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}
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memcpy(state->access, pipeline->access, sizeof(struct lvp_access_info) * 5); //4 vertex stages + fragment
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memset(dynamic_states, 0, sizeof(dynamic_states));
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if (pipeline->graphics_create_info.pDynamicState)
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{
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@ -1219,8 +1236,19 @@ static void fill_image_view_stage(struct rendering_state *state,
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state->iv[p_stage][idx].u.tex.last_layer = 0;
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state->iv[p_stage][idx].u.tex.level = 0;
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}
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state->iv[p_stage][idx].access = PIPE_IMAGE_ACCESS_READ_WRITE;
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state->iv[p_stage][idx].shader_access = PIPE_IMAGE_ACCESS_READ_WRITE;
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assert(idx < 32);
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state->iv[p_stage][idx].access = 0;
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state->iv[p_stage][idx].shader_access = 0;
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if (state->access[stage].images_read & BITFIELD_BIT(idx)) {
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state->iv[p_stage][idx].access |= PIPE_IMAGE_ACCESS_READ;
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state->iv[p_stage][idx].shader_access |= PIPE_IMAGE_ACCESS_READ;
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}
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if (state->access[stage].images_written & BITFIELD_BIT(idx)) {
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state->iv[p_stage][idx].access |= PIPE_IMAGE_ACCESS_WRITE;
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state->iv[p_stage][idx].shader_access |= PIPE_IMAGE_ACCESS_WRITE;
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}
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if (state->num_shader_images[p_stage] <= idx)
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state->num_shader_images[p_stage] = idx + 1;
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