intel/compiler: Add helpers for LSC message descriptors
v2 (Jason Ekstrand): - Squash all the similar patches together - Re-arrange and rename some things to be more consistent - Add a lsc_opcode_has_cmask helper - Drop is_one_addr_reg v3 (Jason Ekstrand): - Add transpose - Re-order arguments to make more logical sense - Switch from `write` to `has_dest` Co-authored-by: Mark Janes <mark.a.janes@intel.com> Co-authored-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
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@ -671,6 +671,13 @@ brw_mdc_cmask(unsigned num_channels)
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return 0xf & (0xf << num_channels);
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}
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static inline unsigned
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lsc_cmask(unsigned num_channels)
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{
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assert(num_channels > 0 && num_channels <= 4);
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return BITSET_MASK(num_channels);
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}
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static inline uint32_t
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brw_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo,
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unsigned exec_size, /**< 0 for SIMD4x2 */
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@ -1154,6 +1161,114 @@ brw_fb_write_desc_coarse_write(const struct intel_device_info *devinfo,
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return GET_BITS(desc, 18, 18);
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}
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static inline bool
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lsc_opcode_has_cmask(enum lsc_opcode opcode)
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{
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return opcode == LSC_OP_LOAD_CMASK || opcode == LSC_OP_STORE_CMASK;
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}
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static inline uint32_t
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lsc_data_size_bytes(enum lsc_data_size data_size)
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{
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switch (data_size) {
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case LSC_DATA_SIZE_D8:
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return 1;
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case LSC_DATA_SIZE_D16:
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return 2;
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case LSC_DATA_SIZE_D32:
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case LSC_DATA_SIZE_D8U32:
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case LSC_DATA_SIZE_D16U32:
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case LSC_DATA_SIZE_D16BF32:
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return 4;
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case LSC_DATA_SIZE_D64:
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return 8;
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default:
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unreachable("Unsupported data payload size.");
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}
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}
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static inline uint32_t
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lsc_addr_size_bytes(enum lsc_addr_size addr_size)
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{
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switch (addr_size) {
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case LSC_ADDR_SIZE_A16: return 2;
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case LSC_ADDR_SIZE_A32: return 4;
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case LSC_ADDR_SIZE_A64: return 8;
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default:
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unreachable("Unsupported address size.");
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}
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}
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static inline uint32_t
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lsc_vector_length(enum lsc_vect_size vect_size)
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{
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switch (vect_size) {
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case LSC_VECT_SIZE_V1: return 1;
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case LSC_VECT_SIZE_V2: return 2;
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case LSC_VECT_SIZE_V3: return 3;
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case LSC_VECT_SIZE_V4: return 4;
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case LSC_VECT_SIZE_V8: return 8;
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case LSC_VECT_SIZE_V16: return 16;
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case LSC_VECT_SIZE_V32: return 32;
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case LSC_VECT_SIZE_V64: return 64;
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default:
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unreachable("Unsupported size of vector");
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}
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}
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static inline enum lsc_vect_size
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lsc_vect_size(unsigned vect_size)
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{
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switch(vect_size) {
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case 1: return LSC_VECT_SIZE_V1;
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case 2: return LSC_VECT_SIZE_V2;
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case 3: return LSC_VECT_SIZE_V3;
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case 4: return LSC_VECT_SIZE_V4;
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case 8: return LSC_VECT_SIZE_V8;
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case 16: return LSC_VECT_SIZE_V16;
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case 32: return LSC_VECT_SIZE_V32;
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case 64: return LSC_VECT_SIZE_V64;
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default:
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unreachable("Unsupported vector size for dataport");
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}
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}
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static inline uint32_t
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lsc_msg_desc(UNUSED const struct intel_device_info *devinfo,
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enum lsc_opcode opcode, unsigned simd_size,
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enum lsc_addr_surface_type addr_type,
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enum lsc_addr_size addr_sz, unsigned num_coordinates,
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enum lsc_data_size data_sz, unsigned num_channels,
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bool transpose, unsigned cache_ctrl, bool has_dest)
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{
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assert(devinfo->has_lsc);
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unsigned dest_length = !has_dest ? 0 :
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DIV_ROUND_UP(lsc_data_size_bytes(data_sz) * num_channels * simd_size,
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REG_SIZE);
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unsigned src0_length =
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DIV_ROUND_UP(lsc_addr_size_bytes(addr_sz) * num_coordinates * simd_size,
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REG_SIZE);
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unsigned msg_desc =
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SET_BITS(opcode, 5, 0) |
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SET_BITS(addr_sz, 8, 7) |
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SET_BITS(data_sz, 11, 9) |
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SET_BITS(transpose, 15, 15) |
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SET_BITS(cache_ctrl, 19, 17) |
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SET_BITS(dest_length, 24, 20) |
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SET_BITS(src0_length, 28, 25) |
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SET_BITS(addr_type, 30, 29);
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if (lsc_opcode_has_cmask(opcode))
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msg_desc |= SET_BITS(lsc_cmask(num_channels), 15, 12);
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else
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msg_desc |= SET_BITS(lsc_vect_size(num_channels), 14, 12);
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return msg_desc;
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}
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static inline uint32_t
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lsc_fence_msg_desc(UNUSED const struct intel_device_info *devinfo,
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enum lsc_fence_scope scope,
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@ -1169,6 +1284,46 @@ lsc_fence_msg_desc(UNUSED const struct intel_device_info *devinfo,
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SET_BITS(LSC_ADDR_SURFTYPE_FLAT, 30, 29);
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}
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static inline uint32_t
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lsc_bti_ex_desc(const struct intel_device_info *devinfo, unsigned bti)
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{
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assert(devinfo->has_lsc);
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return SET_BITS(bti, 31, 24) |
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SET_BITS(0, 23, 12); /* base offset */
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}
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static inline unsigned
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lsc_bti_ex_desc_index(const struct intel_device_info *devinfo,
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uint32_t ex_desc)
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{
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assert(devinfo->has_lsc);
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return GET_BITS(ex_desc, 31, 24);
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}
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static inline unsigned
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lsc_flat_ex_desc_base_offset(const struct intel_device_info *devinfo,
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uint32_t ex_desc)
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{
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assert(devinfo->has_lsc);
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return GET_BITS(ex_desc, 31, 12);
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}
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static inline uint32_t
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lsc_bss_ex_desc(const struct intel_device_info *devinfo,
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unsigned surface_state_index)
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{
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assert(devinfo->has_lsc);
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return SET_BITS(surface_state_index, 31, 6);
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}
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static inline unsigned
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lsc_bss_ex_desc_index(const struct intel_device_info *devinfo,
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uint32_t ex_desc)
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{
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assert(devinfo->has_lsc);
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return GET_BITS(ex_desc, 31, 6);
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}
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static inline uint32_t
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brw_mdc_sm2(unsigned exec_size)
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{
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