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intel/compiler: Improve fix_3src_operand() 

Allow ATTR and IMM sources unconditionally (ATTR are just GRFs, IMM will
be handled by opt_combine_constants(). Both are already allowed by
opt_copy_propagation().

Also allow FIXED_GRF if the regioning is 8,8,1. Could also allow other
stride=1 regions (e.g., 4,4,1) and scalar regions but I don't think
those occur. This is sufficient to allow a pass added in a future commit
(fs_visitor::lower_linterp) to avoid emitting extra MOV instructions.

I removed the 'src.stride > 1' case because it seems wrong: 3-src
instructions on Gen6-9 are align16-only and can only do stride=1 or
stride=0. A run through Jenkins with an assert(src.stride <= 1) never
triggers, so it seems that it was dead code.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
This commit is contained in:
Matt Turner 2019-04-18 14:29:03 -07:00 committed by Rafael Antognolli
parent 8aae7a3998
commit 4ec258ac3c
1 changed files with 18 additions and 5 deletions
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23
src/intel/compiler/brw_fs_builder.h
View File

@ -733,13 +733,26 @@ namespace brw {
src_reg
fix_3src_operand(const src_reg &src) const
{
if (src.file == VGRF || src.file == UNIFORM || src.stride > 1) {
switch (src.file) {
case FIXED_GRF:
/* FINISHME: Could handle scalar region, other stride=1 regions */
if (src.vstride != BRW_VERTICAL_STRIDE_8 ||
src.width != BRW_WIDTH_8 ||
src.hstride != BRW_HORIZONTAL_STRIDE_1)
break;
/* fallthrough */
case ATTR:
case VGRF:
case UNIFORM:
case IMM:
return src;
} else {
dst_reg expanded = vgrf(src.type);
MOV(expanded, src);
return expanded;
default:
break;
}
dst_reg expanded = vgrf(src.type);
MOV(expanded, src);
return expanded;
}
/**