radv: Move normal (non-empty) queue submit to a separate function.
Also move the preamble update into this function, as that is only needed by this code path and not needed for empty submits. With this change, the goal is to make radv_queue_submit easier to read and understand. This prepares it for future work when we'll add the capability to submit to multiple queues at the same time. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16358>
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@ -4551,10 +4551,10 @@ radv_queue_submit_empty(struct radv_queue *queue, struct vk_queue_submit *submis
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}
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static VkResult
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radv_queue_submit(struct vk_queue *vqueue, struct vk_queue_submit *submission)
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radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submission)
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{
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struct radv_queue *queue = (struct radv_queue *)vqueue;
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struct radeon_winsys_ctx *ctx = queue->hw_ctx;
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enum amd_ip_type ring = radv_queue_ring(queue);
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uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
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bool can_patch = true;
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uint32_t advance;
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@ -4562,14 +4562,75 @@ radv_queue_submit(struct vk_queue *vqueue, struct vk_queue_submit *submission)
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struct radeon_cmdbuf *initial_preamble_cs = NULL;
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struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
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struct radeon_cmdbuf *continue_preamble_cs = NULL;
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enum amd_ip_type ring = radv_queue_ring(queue);
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result =
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radv_get_preambles(queue, submission->command_buffers, submission->command_buffer_count,
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&initial_flush_preamble_cs, &initial_preamble_cs, &continue_preamble_cs);
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if (result != VK_SUCCESS)
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return result;
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if (queue->device->trace_bo)
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simple_mtx_lock(&queue->device->trace_mtx);
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struct radeon_cmdbuf **cs_array =
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malloc(sizeof(struct radeon_cmdbuf *) * (submission->command_buffer_count));
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if (!cs_array)
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goto fail;
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for (uint32_t j = 0; j < submission->command_buffer_count; j++) {
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struct radv_cmd_buffer *cmd_buffer = (struct radv_cmd_buffer *)submission->command_buffers[j];
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assert(cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
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cs_array[j] = cmd_buffer->cs;
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if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
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can_patch = false;
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cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
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}
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for (uint32_t j = 0; j < submission->command_buffer_count; j += advance) {
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/* For fences on the same queue/vm amdgpu doesn't wait till all processing is finished
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* before starting the next cmdbuffer, so we need to do it here. */
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bool need_wait = !j && submission->wait_count > 0;
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struct radeon_cmdbuf *initial_preamble =
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need_wait ? initial_flush_preamble_cs : initial_preamble_cs;
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advance = MIN2(max_cs_submission, submission->command_buffer_count - j);
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bool last_submit = j + advance == submission->command_buffer_count;
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if (queue->device->trace_bo)
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*queue->device->trace_id_ptr = 0;
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result = queue->device->ws->cs_submit(
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ctx, ring, queue->vk.index_in_family, cs_array + j, advance, initial_preamble,
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continue_preamble_cs, j == 0 ? submission->wait_count : 0, submission->waits,
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last_submit ? submission->signal_count : 0, submission->signals, can_patch);
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if (result != VK_SUCCESS)
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goto fail;
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if (queue->device->trace_bo) {
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radv_check_gpu_hangs(queue, cs_array[j]);
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}
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if (queue->device->tma_bo) {
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radv_check_trap_handler(queue);
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}
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}
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fail:
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free(cs_array);
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if (queue->device->trace_bo)
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simple_mtx_unlock(&queue->device->trace_mtx);
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return result;
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}
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static VkResult
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radv_queue_submit(struct vk_queue *vqueue, struct vk_queue_submit *submission)
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{
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struct radv_queue *queue = (struct radv_queue *)vqueue;
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VkResult result;
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result = radv_queue_submit_bind_sparse_memory(queue->device, submission);
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if (result != VK_SUCCESS)
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goto fail;
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@ -4580,59 +4641,7 @@ radv_queue_submit(struct vk_queue *vqueue, struct vk_queue_submit *submission)
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if (!submission->command_buffer_count) {
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result = radv_queue_submit_empty(queue, submission);
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} else {
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if (queue->device->trace_bo)
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simple_mtx_lock(&queue->device->trace_mtx);
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struct radeon_cmdbuf **cs_array =
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malloc(sizeof(struct radeon_cmdbuf *) * (submission->command_buffer_count));
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for (uint32_t j = 0; j < submission->command_buffer_count; j++) {
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struct radv_cmd_buffer *cmd_buffer =
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(struct radv_cmd_buffer *)submission->command_buffers[j];
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assert(cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
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cs_array[j] = cmd_buffer->cs;
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if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
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can_patch = false;
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cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
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}
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for (uint32_t j = 0; j < submission->command_buffer_count; j += advance) {
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/* For fences on the same queue/vm amdgpu doesn't wait till all processing is finished
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* before starting the next cmdbuffer, so we need to do it here. */
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bool need_wait = !j && submission->wait_count > 0;
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struct radeon_cmdbuf *initial_preamble =
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need_wait ? initial_flush_preamble_cs : initial_preamble_cs;
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advance = MIN2(max_cs_submission, submission->command_buffer_count - j);
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bool last_submit = j + advance == submission->command_buffer_count;
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if (queue->device->trace_bo)
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*queue->device->trace_id_ptr = 0;
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result = queue->device->ws->cs_submit(
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ctx, ring, queue->vk.index_in_family, cs_array + j, advance, initial_preamble,
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continue_preamble_cs, j == 0 ? submission->wait_count : 0, submission->waits,
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last_submit ? submission->signal_count : 0, submission->signals, can_patch);
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if (result != VK_SUCCESS) {
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free(cs_array);
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if (queue->device->trace_bo)
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simple_mtx_unlock(&queue->device->trace_mtx);
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goto fail;
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}
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if (queue->device->trace_bo) {
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radv_check_gpu_hangs(queue, cs_array[j]);
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}
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if (queue->device->tma_bo) {
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radv_check_trap_handler(queue);
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}
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}
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free(cs_array);
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if (queue->device->trace_bo)
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simple_mtx_unlock(&queue->device->trace_mtx);
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result = radv_queue_submit_normal(queue, submission);
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}
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fail:
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