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i965: Enable INTEL_shader_integer_functions2 on Gen8+ 

v2: Use new lower_hadd64 and lower_usub_sat64 flags.

v3: Enable SPIR-V capability.

v4: Move lowering options to COMMON_SCALAR_OPTIONS.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
This commit is contained in:
Ian Romanick 2018-09-11 16:50:06 -07:00 committed by Marge Bot
parent 4fcddb55f2
commit 4e9079d0c7
3 changed files with 8 additions and 0 deletions
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2
src/intel/compiler/brw_compiler.c
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@ -61,6 +61,8 @@
.lower_unpack_snorm_4x8 = true, \
.lower_unpack_unorm_2x16 = true, \
.lower_unpack_unorm_4x8 = true, \
.lower_usub_sat64 = true, \
.lower_hadd64 = true, \
.max_unroll_iterations = 32
static const struct nir_shader_compiler_options scalar_nir_options = {

1
src/mesa/drivers/dri/i965/brw_context.c
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@ -411,6 +411,7 @@ brw_initialize_spirv_supported_capabilities(struct brw_context *brw)
ctx->Const.SpirVCapabilities.tessellation = true;
ctx->Const.SpirVCapabilities.transform_feedback = devinfo->gen >= 7;
ctx->Const.SpirVCapabilities.variable_pointers = true;
ctx->Const.SpirVCapabilities.integer_functions2 = devinfo->gen >= 8;
}
static void

5
src/mesa/drivers/dri/i965/intel_extensions.c
View File

@ -320,6 +320,11 @@ intelInitExtensions(struct gl_context *ctx)
/* requires ARB_gpu_shader_int64 */
ctx->Extensions.ARB_shader_ballot = true;
ctx->Extensions.ARB_ES3_2_compatibility = true;
/* Currently only implemented in the scalar backend, so only enable for
* Gen8+. Eventually Gen6+ could be supported.
*/
ctx->Extensions.INTEL_shader_integer_functions2 = true;
}
if (devinfo->gen >= 9) {