freedreno/ir3: Clean up instruction creation
Convert everything remaining over to the version which takes # of register (src + dst) and drop the ir3_instr_create2() version. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
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d968f46997
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4e272003b1
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@ -232,7 +232,7 @@ static int emit_cat2(struct ir3_instruction *instr, void *ptr,
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{
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struct ir3_register *dst = instr->regs[0];
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struct ir3_register *src1 = instr->regs[1];
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struct ir3_register *src2 = instr->regs[2];
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struct ir3_register *src2 = (instr->regs_count > 2) ? instr->regs[2] : NULL;
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instr_cat2_t *cat2 = ptr;
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unsigned absneg = ir3_cat2_absneg(instr->opc);
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@ -1141,7 +1141,7 @@ static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
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return instr;
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}
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struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
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struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
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opc_t opc, int nreg)
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{
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struct ir3_instruction *instr = instr_create(block, nreg);
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@ -1151,14 +1151,6 @@ struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
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return instr;
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}
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struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc)
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{
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/* NOTE: we could be slightly more clever, at least for non-meta,
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* and choose # of regs based on category.
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*/
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return ir3_instr_create2(block, opc, 4);
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}
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struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
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{
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struct ir3_instruction *new_instr = instr_create(instr->block,
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@ -580,8 +580,7 @@ void * ir3_alloc(struct ir3 *shader, int sz);
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struct ir3_block * ir3_block_create(struct ir3 *shader);
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struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
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struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
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struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
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opc_t opc, int nreg);
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struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
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void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
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@ -1386,7 +1385,7 @@ create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
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struct ir3_instruction *mov;
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unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
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mov = ir3_instr_create(block, OPC_MOV);
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mov = ir3_instr_create(block, OPC_MOV, 2);
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mov->cat1.src_type = type;
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mov->cat1.dst_type = type;
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__ssa_dst(mov)->flags |= flags;
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@ -1407,7 +1406,7 @@ create_uniform_typed(struct ir3_block *block, unsigned n, type_t type)
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struct ir3_instruction *mov;
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unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
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mov = ir3_instr_create(block, OPC_MOV);
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mov = ir3_instr_create(block, OPC_MOV, 2);
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mov->cat1.src_type = type;
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mov->cat1.dst_type = type;
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__ssa_dst(mov)->flags |= flags;
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@ -1428,7 +1427,7 @@ create_uniform_indirect(struct ir3_block *block, int n, type_t type,
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{
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struct ir3_instruction *mov;
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mov = ir3_instr_create(block, OPC_MOV);
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mov = ir3_instr_create(block, OPC_MOV, 2);
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mov->cat1.src_type = type;
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mov->cat1.dst_type = type;
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__ssa_dst(mov);
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@ -1442,7 +1441,7 @@ create_uniform_indirect(struct ir3_block *block, int n, type_t type,
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static inline struct ir3_instruction *
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ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
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{
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struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
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struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV, 2);
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unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
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__ssa_dst(instr)->flags |= flags;
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@ -1462,7 +1461,7 @@ static inline struct ir3_instruction *
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ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
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type_t src_type, type_t dst_type)
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{
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struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
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struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV, 2);
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unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
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unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
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@ -1479,7 +1478,7 @@ ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
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static inline struct ir3_instruction *
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ir3_MOVMSK(struct ir3_block *block, unsigned components)
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{
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struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOVMSK);
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struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOVMSK, 1);
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struct ir3_register *dst = __ssa_dst(instr);
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dst->flags |= IR3_REG_SHARED;
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@ -1490,7 +1489,7 @@ ir3_MOVMSK(struct ir3_block *block, unsigned components)
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static inline struct ir3_instruction *
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ir3_NOP(struct ir3_block *block)
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{
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return ir3_instr_create(block, OPC_NOP);
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return ir3_instr_create(block, OPC_NOP, 0);
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}
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#define IR3_INSTR_0 0
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@ -1500,7 +1499,7 @@ static inline struct ir3_instruction * \
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ir3_##name(struct ir3_block *block) \
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{ \
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struct ir3_instruction *instr = \
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ir3_instr_create(block, opc); \
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ir3_instr_create(block, opc, 1); \
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instr->flags |= flag; \
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return instr; \
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}
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@ -1513,7 +1512,7 @@ ir3_##name(struct ir3_block *block, \
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struct ir3_instruction *a, unsigned aflags) \
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{ \
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struct ir3_instruction *instr = \
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ir3_instr_create(block, opc); \
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ir3_instr_create(block, opc, 2); \
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__ssa_dst(instr); \
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__ssa_src(instr, a, aflags); \
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instr->flags |= flag; \
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@ -1529,7 +1528,7 @@ ir3_##name(struct ir3_block *block, \
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struct ir3_instruction *b, unsigned bflags) \
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{ \
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struct ir3_instruction *instr = \
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ir3_instr_create(block, opc); \
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ir3_instr_create(block, opc, 3); \
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__ssa_dst(instr); \
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__ssa_src(instr, a, aflags); \
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__ssa_src(instr, b, bflags); \
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@ -1547,7 +1546,7 @@ ir3_##name(struct ir3_block *block, \
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struct ir3_instruction *c, unsigned cflags) \
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{ \
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struct ir3_instruction *instr = \
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ir3_instr_create2(block, opc, 4); \
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ir3_instr_create(block, opc, 4); \
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__ssa_dst(instr); \
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__ssa_src(instr, a, aflags); \
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__ssa_src(instr, b, bflags); \
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@ -1567,7 +1566,7 @@ ir3_##name(struct ir3_block *block, \
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struct ir3_instruction *d, unsigned dflags) \
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{ \
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struct ir3_instruction *instr = \
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ir3_instr_create2(block, opc, 5); \
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ir3_instr_create(block, opc, 5); \
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__ssa_dst(instr); \
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__ssa_src(instr, a, aflags); \
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__ssa_src(instr, b, bflags); \
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@ -1684,8 +1683,19 @@ ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
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struct ir3_instruction *src0, struct ir3_instruction *src1)
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{
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struct ir3_instruction *sam;
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unsigned nreg = 1; /* dst */
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sam = ir3_instr_create(block, opc);
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if (flags & IR3_INSTR_S2EN) {
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nreg++;
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}
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if (src0) {
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nreg++;
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}
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if (src1) {
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nreg++;
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}
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sam = ir3_instr_create(block, opc, nreg);
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sam->flags |= flags;
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__ssa_dst(sam)->wrmask = wrmask;
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if (flags & IR3_INSTR_S2EN) {
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@ -1763,9 +1773,6 @@ INSTR4F(G, STG)
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INSTR0(BAR)
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INSTR0(FENCE)
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/* meta instructions: */
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INSTR0(META_TEX_PREFETCH);
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/* ************************************************************************* */
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#include "regmask.h"
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@ -387,7 +387,7 @@ get_atomic_dest_mov(struct ir3_instruction *atomic)
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return atomic->data;
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/* We are already out of SSA here, so we can't use the nice builders: */
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mov = ir3_instr_create(atomic->block, OPC_MOV);
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mov = ir3_instr_create(atomic->block, OPC_MOV, 2);
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ir3_reg_create(mov, 0, 0); /* dst */
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ir3_reg_create(mov, 0, 0); /* src */
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@ -55,7 +55,7 @@ create_input(struct ir3_context *ctx, unsigned compmask)
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{
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struct ir3_instruction *in;
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in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
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in = ir3_instr_create(ctx->in_block, OPC_META_INPUT, 1);
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in->input.sysval = ~0;
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__ssa_dst(in)->wrmask = compmask;
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@ -2480,9 +2480,8 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
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compile_assert(ctx, tex->src[idx].src.is_ssa);
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sam = ir3_META_TEX_PREFETCH(b);
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__ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
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__ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0);
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sam = ir3_SAM(b, opc, type, MASK(ncomp), 0, NULL,
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get_barycentric(ctx, IJ_PERSP_PIXEL), 0);
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sam->prefetch.input_offset =
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ir3_nir_coord_offset(tex->src[idx].src.ssa);
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/* make sure not to add irrelevant flags like S2EN */
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@ -308,7 +308,7 @@ ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr,
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unsigned flags = dest_flags(arr[0]);
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collect = ir3_instr_create2(block, OPC_META_COLLECT, 1 + arrsz);
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collect = ir3_instr_create(block, OPC_META_COLLECT, 1 + arrsz);
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__ssa_dst(collect)->flags |= flags;
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for (unsigned i = 0; i < arrsz; i++) {
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struct ir3_instruction *elem = arr[i];
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@ -382,7 +382,7 @@ ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
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for (int i = 0, j = 0; i < n; i++) {
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struct ir3_instruction *split =
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ir3_instr_create(block, OPC_META_SPLIT);
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ir3_instr_create(block, OPC_META_SPLIT, 2);
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__ssa_dst(split)->flags |= flags;
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__ssa_src(split, src, flags);
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split->split.off = i + base;
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@ -584,7 +584,7 @@ ir3_create_array_load(struct ir3_context *ctx, struct ir3_array *arr, int n,
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struct ir3_register *src;
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unsigned flags = 0;
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mov = ir3_instr_create(block, OPC_MOV);
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mov = ir3_instr_create(block, OPC_MOV, 2);
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if (arr->half) {
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mov->cat1.src_type = TYPE_U16;
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mov->cat1.dst_type = TYPE_U16;
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@ -645,7 +645,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
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return;
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}
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mov = ir3_instr_create(block, OPC_MOV);
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mov = ir3_instr_create(block, OPC_MOV, 2);
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if (arr->half) {
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mov->cat1.src_type = TYPE_U16;
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mov->cat1.dst_type = TYPE_U16;
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@ -297,7 +297,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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struct ir3_instruction *baryf;
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/* (ss)bary.f (ei)r63.x, 0, r0.x */
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baryf = ir3_instr_create(block, OPC_BARY_F);
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baryf = ir3_instr_create(block, OPC_BARY_F, 3);
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ir3_reg_create(baryf, regid(63, 0), 0);
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ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
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ir3_reg_create(baryf, regid(0, 0), 0);
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@ -323,7 +323,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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struct ir3_instruction *baryf;
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/* (ss)bary.f (ei)r63.x, 0, r0.x */
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baryf = ir3_instr_create(block, OPC_BARY_F);
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baryf = ir3_instr_create(block, OPC_BARY_F, 3);
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ir3_reg_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI;
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ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
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ir3_reg_create(baryf, regid(0, 0), 0);
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@ -667,7 +667,7 @@ kill_sched(struct ir3 *ir, struct ir3_shader_variant *so)
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if (instr->opc != OPC_KILL)
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continue;
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struct ir3_instruction *br = ir3_instr_create(block, OPC_B);
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struct ir3_instruction *br = ir3_instr_create(block, OPC_B, 2);
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br->regs[1] = instr->regs[1];
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br->cat0.target =
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list_last_entry(&ir->block_list, struct ir3_block, node);
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@ -79,7 +79,7 @@ int ir3_yyget_lineno(void);
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static struct ir3_instruction * new_instr(opc_t opc)
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{
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instr = ir3_instr_create(block, opc);
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instr = ir3_instr_create(block, opc, 5);
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instr->flags = iflags.flags;
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instr->repeat = iflags.repeat;
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instr->nop = iflags.nop;
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@ -139,7 +139,7 @@ regs_to_ssa(struct ir3 *ir)
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unsigned nsrc = 1 + instr->repeat;
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unsigned flags = src->regs[0]->flags & IR3_REG_HALF;
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struct ir3_instruction *collect =
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ir3_instr_create2(block, OPC_META_COLLECT, 1 + nsrc);
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ir3_instr_create(block, OPC_META_COLLECT, 1 + nsrc);
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__ssa_dst(collect)->flags |= flags;
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for (unsigned i = 0; i < nsrc; i++)
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__ssa_src(collect, regfile[regn(reg) + i], flags);
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@ -159,7 +159,7 @@ regs_to_ssa(struct ir3 *ir)
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for (unsigned i = 0; i < ndst; i++) {
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struct ir3_instruction *split =
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ir3_instr_create(block, OPC_META_SPLIT);
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ir3_instr_create(block, OPC_META_SPLIT, 2);
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__ssa_dst(split)->flags |= flags;
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__ssa_src(split, instr, flags);
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split->split.off = i;
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