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radeonsi: Fix off-by-one for maximum vertex element index in some cases 

In cases where the vertex element size is smaller than the vertex buffer
stride, the previous calculation could end up 1 too low. This would result
in the GPU using index 0 instead of the maximum index for those elements,
which would be visible as intermittent distorted triangles.

NOTE: This is a candidate for the 9.1 branch.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer 2013-03-12 12:34:37 +01:00 committed by Michel Dänzer
parent 8aa8b0539e
commit 4dca602521
1 changed files with 8 additions and 2 deletions
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10
src/gallium/drivers/radeonsi/si_state_draw.c
View File

@ -448,8 +448,14 @@ static void si_vertex_buffer_update(struct r600_context *rctx)
si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vb->stride)));
si_pm4_sh_data_add(pm4, (vb->buffer->width0 - vb->buffer_offset) /
MAX2(vb->stride, 1));
if (vb->stride)
/* Round up by rounding down and adding 1 */
si_pm4_sh_data_add(pm4,
(vb->buffer->width0 - offset -
util_format_get_blocksize(ve->src_format)) /
vb->stride + 1);
else
si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
if (!bound[ve->vertex_buffer_index]) {