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isl: Add isl_dev->mocs.blitter_{src,dst} fields 

These will be used for XY_BLOCK_COPY_BLT on XeHP.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>
This commit is contained in:
Kenneth Graunke 2021-11-28 00:55:48 -08:00 committed by Marge Bot
parent abd71630fc
commit 4d4f57b15c
2 changed files with 26 additions and 0 deletions
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24
src/intel/isl/isl.c
View File

@ -103,6 +103,30 @@ isl_device_setup_mocs(struct isl_device *dev)
/* L3CC=WB; BSpec: 45101 */
dev->mocs.internal = 3 << 1;
dev->mocs.external = 3 << 1;
/* XY_BLOCK_COPY_BLT MOCS fields have programming notes which say:
*
* "Destination MOCS value, which is used to program MOCS index
* for writing to memory, should select a MOCS register having
* "L3 Cacheability Control" programmed as uncacheable(UC) and
* "Global GO" parameter set as GOMemory (pushes GO point to
* memory). The MOCS Register may have L3 Lookup programmed as
* UCL3LKDIS for better efficiency."
*
* The GO:Memory setting requires us to use MOCS 1 or 2. MOCS 2
* has LKUP set to 0 and is marked "Non-Coherent", which we assume
* is probably the "better efficiency" they mention...
*
* "Source MOCS value, which is used to program MOCS index for
* reading from memory, should select a MOCS register having
* "L3 Cacheability Control" programmed as uncacheable(UC).
* The MOCS Register may have L3 Lookup programmed as UCL3LKDIS
* for better efficiency."
*
* Any MOCS except 3 should work. We use MOCS 2...
*/
dev->mocs.blitter_dst = 2 << 1;
dev->mocs.blitter_src = 2 << 1;
} else if (dev->info->platform == INTEL_PLATFORM_DG1) {
/* L3CC=WB */
dev->mocs.internal = 5 << 1;

2
src/intel/isl/isl.h
View File

@ -1273,6 +1273,8 @@ struct isl_device {
uint32_t internal;
uint32_t external;
uint32_t l1_hdc_l3_llc;
uint32_t blitter_src;
uint32_t blitter_dst;
} mocs;
};