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i965/gen9: Modify the conditions to use blitter on skl+ 

Conditions modified allow skl+ to use blitter:
 - for all tiling formats
 - to write data to YF/YS tiled surfaces

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Anuj Phogat 2015-03-24 16:07:40 -07:00
parent 0bf037c0fe
commit 4d2a7f5111
1 changed files with 9 additions and 3 deletions
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12
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
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@ -2697,13 +2697,17 @@ use_intel_mipree_map_blit(struct brw_context *brw,
{
if (brw->has_llc &&
/* It's probably not worth swapping to the blit ring because of
* all the overhead involved.
* all the overhead involved. But, we must use blitter for the
* surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
*/
!(mode & GL_MAP_WRITE_BIT) &&
(!(mode & GL_MAP_WRITE_BIT) ||
mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) &&
!mt->compressed &&
(mt->tiling == I915_TILING_X ||
/* Prior to Sandybridge, the blitter can't handle Y tiling */
(brw->gen >= 6 && mt->tiling == I915_TILING_Y)) &&
(brw->gen >= 6 && mt->tiling == I915_TILING_Y) ||
/* Fast copy blit on skl+ supports all tiling formats. */
brw->gen >= 9) &&
can_blit_slice(mt, level, slice))
return true;
@ -2772,6 +2776,8 @@ intel_miptree_map(struct brw_context *brw,
intel_miptree_map_movntdqa(brw, mt, map, level, slice);
#endif
} else {
/* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
assert(mt->tr_mode == INTEL_MIPTREE_TRMODE_NONE);
intel_miptree_map_gtt(brw, mt, map, level, slice);
}