anv: Count image param entries rather than images
This is what we're actually storing in the descriptor set and consuming when we bind surface states. This commit renames image_count to image_param_count a few places and moves the decision to not count image params on gen9+ into anv_descriptor_set.c when we build the layout. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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@ -150,7 +150,7 @@ VkResult anv_CreateDescriptorSetLayout(
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uint32_t sampler_count[MESA_SHADER_STAGES] = { 0, };
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uint32_t surface_count[MESA_SHADER_STAGES] = { 0, };
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uint32_t image_count[MESA_SHADER_STAGES] = { 0, };
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uint32_t image_param_count[MESA_SHADER_STAGES] = { 0, };
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uint32_t buffer_view_count = 0;
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uint32_t dynamic_offset_count = 0;
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@ -245,9 +245,12 @@ VkResult anv_CreateDescriptorSetLayout(
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switch (binding->descriptorType) {
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case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
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case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
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anv_foreach_stage(s, binding->stageFlags) {
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set_layout->binding[b].stage[s].image_index = image_count[s];
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image_count[s] += binding->descriptorCount;
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if (device->info.gen < 9) {
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anv_foreach_stage(s, binding->stageFlags) {
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set_layout->binding[b].stage[s].image_param_index =
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image_param_count[s];
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image_param_count[s] += binding->descriptorCount;
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}
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}
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break;
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default:
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@ -521,23 +521,23 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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}
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}
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if (binding->stage[stage].image_index >= 0) {
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state.set[set].image_offsets[b] = map->image_count;
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map->image_count += binding->array_size;
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if (binding->stage[stage].image_param_index >= 0) {
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state.set[set].image_offsets[b] = map->image_param_count;
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map->image_param_count += binding->array_size;
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}
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}
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}
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if (map->image_count > 0 && pdevice->compiler->devinfo->gen < 9) {
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assert(map->image_count <= MAX_GEN8_IMAGES);
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if (map->image_param_count > 0) {
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assert(map->image_param_count <= MAX_GEN8_IMAGES);
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assert(shader->num_uniforms == prog_data->nr_params * 4);
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state.first_image_uniform = shader->num_uniforms;
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uint32_t *param = brw_stage_prog_data_add_params(prog_data,
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map->image_count *
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map->image_param_count *
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BRW_IMAGE_PARAM_SIZE);
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struct anv_push_constants *null_data = NULL;
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const struct brw_image_param *image_param = null_data->images;
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for (uint32_t i = 0; i < map->image_count; i++) {
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for (uint32_t i = 0; i < map->image_param_count; i++) {
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setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
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(uintptr_t)image_param->offset, 2);
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setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
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@ -554,7 +554,8 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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}
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assert(param == prog_data->param + prog_data->nr_params);
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shader->num_uniforms += map->image_count * BRW_IMAGE_PARAM_SIZE * 4;
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shader->num_uniforms += map->image_param_count *
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BRW_IMAGE_PARAM_SIZE * 4;
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assert(shader->num_uniforms == prog_data->nr_params * 4);
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}
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@ -154,7 +154,7 @@ anv_shader_bin_write_to_blob(const struct anv_shader_bin *shader,
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blob_write_uint32(blob, shader->bind_map.surface_count);
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blob_write_uint32(blob, shader->bind_map.sampler_count);
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blob_write_uint32(blob, shader->bind_map.image_count);
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blob_write_uint32(blob, shader->bind_map.image_param_count);
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blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
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shader->bind_map.surface_count *
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sizeof(*shader->bind_map.surface_to_descriptor));
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@ -194,7 +194,7 @@ anv_shader_bin_create_from_blob(struct anv_device *device,
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struct anv_pipeline_bind_map bind_map;
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bind_map.surface_count = blob_read_uint32(blob);
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bind_map.sampler_count = blob_read_uint32(blob);
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bind_map.image_count = blob_read_uint32(blob);
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bind_map.image_param_count = blob_read_uint32(blob);
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bind_map.surface_to_descriptor = (void *)
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blob_read_bytes(blob, bind_map.surface_count *
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sizeof(*bind_map.surface_to_descriptor));
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@ -1523,8 +1523,8 @@ struct anv_descriptor_set_binding_layout {
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/* Index into the sampler table for the associated sampler */
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int16_t sampler_index;
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/* Index into the image table for the associated image */
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int16_t image_index;
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/* Index into the image param table for the associated image */
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int16_t image_param_index;
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} stage[MESA_SHADER_STAGES];
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/* Immutable samplers (or NULL if no immutable samplers) */
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@ -2535,7 +2535,7 @@ mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
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struct anv_pipeline_bind_map {
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uint32_t surface_count;
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uint32_t sampler_count;
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uint32_t image_count;
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uint32_t image_param_count;
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struct anv_pipeline_binding * surface_to_descriptor;
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struct anv_pipeline_binding * sampler_to_descriptor;
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@ -2070,7 +2070,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
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return VK_ERROR_OUT_OF_DEVICE_MEMORY;
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/* We only use push constant space for images before gen9 */
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if (map->image_count > 0 && devinfo->gen < 9) {
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if (map->image_param_count > 0) {
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VkResult result =
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anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, images);
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if (result != VK_SUCCESS)
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@ -2203,14 +2203,17 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
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assert(surface_state.alloc_size);
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add_surface_state_relocs(cmd_buffer, sstate);
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if (devinfo->gen < 9) {
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/* We only need the image params on gen8 and earlier. No image
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* workarounds that require tiling information are required on
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* SKL and above.
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*/
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assert(image < MAX_GEN8_IMAGES);
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struct brw_image_param *image_param =
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&cmd_buffer->state.push_constants[stage]->images[image];
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&cmd_buffer->state.push_constants[stage]->images[image++];
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*image_param =
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desc->image_view->planes[binding->plane].storage_image_param;
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}
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image++;
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break;
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}
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@ -2258,11 +2261,10 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
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if (devinfo->gen < 9) {
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assert(image < MAX_GEN8_IMAGES);
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struct brw_image_param *image_param =
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&cmd_buffer->state.push_constants[stage]->images[image];
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&cmd_buffer->state.push_constants[stage]->images[image++];
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*image_param = desc->buffer_view->storage_image_param;
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}
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image++;
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break;
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default:
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@ -2272,7 +2274,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
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bt_map[s] = surface_state.offset + state_offset;
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}
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assert(image == map->image_count);
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assert(image == map->image_param_count);
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#if GEN_GEN >= 11
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/* The PIPE_CONTROL command description says:
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