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radeonsi: don't allocate DCC for the temporary MSAA resolve surface 

Allocating it has no effect, but it adds overhead (useless DCC clear).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2016-06-06 01:42:46 +02:00
parent c06246501e
commit 4be46c7d9d
3 changed files with 5 additions and 2 deletions
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1
src/gallium/drivers/radeon/r600_pipe_common.h
View File

@ -48,6 +48,7 @@
#define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
#define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
/* Pipeline & streamout query controls. */

3
src/gallium/drivers/radeon/r600_texture.c
View File

@ -263,7 +263,8 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
}
if (rscreen->chip_class >= VI &&
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
surface->flags |= RADEON_SURF_DISABLE_DCC;
if (ptex->bind & PIPE_BIND_SCANOUT) {

3
src/gallium/drivers/radeonsi/si_blit.c
View File

@ -928,7 +928,8 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
templ.depth0 = 1;
templ.array_size = 1;
templ.usage = PIPE_USAGE_DEFAULT;
templ.flags = R600_RESOURCE_FLAG_FORCE_TILING;
templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
R600_RESOURCE_FLAG_DISABLE_DCC;
tmp = ctx->screen->resource_create(ctx->screen, &templ);
if (!tmp)