intel: Use a system value for gl_FragCoord
It's kind-of an anomaly that the Intel drivers are still treating gl_FragCoord as an input. It also makes zero sense because we have to special-case it in the back-end. Because ANV is the only user of nir_lower_wpos_center, we go ahead and just update it to look for nir_intrinsic_load_frag_coord as part of this patch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
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44268b1c72
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4bb6e6817e
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@ -80,19 +80,9 @@ lower_wpos_center_block(nir_builder *b, nir_block *block,
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nir_foreach_instr(instr, block) {
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nir_foreach_instr(instr, block) {
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if (instr->type == nir_instr_type_intrinsic) {
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if (instr->type == nir_instr_type_intrinsic) {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic == nir_intrinsic_load_deref) {
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if (intr->intrinsic == nir_intrinsic_load_frag_coord) {
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nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
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update_fragcoord(b, intr, for_sample_shading);
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if (deref->mode != nir_var_shader_in)
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progress = true;
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continue;
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nir_variable *var = nir_deref_instr_get_variable(deref);
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if (var->data.location == VARYING_SLOT_POS) {
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/* gl_FragCoord should not have array/struct derefs: */
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assert(deref->deref_type == nir_deref_type_var);
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update_fragcoord(b, intr, for_sample_shading);
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progress = true;
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}
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}
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}
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}
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}
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}
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}
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@ -190,6 +190,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_LOAD_CONSTBUF:
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case PIPE_CAP_LOAD_CONSTBUF:
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case PIPE_CAP_NIR_COMPACT_ARRAYS:
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case PIPE_CAP_NIR_COMPACT_ARRAYS:
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case PIPE_CAP_DRAW_PARAMETERS:
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case PIPE_CAP_DRAW_PARAMETERS:
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case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
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case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
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case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
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case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
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case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
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case PIPE_CAP_INVALIDATE_BUFFER:
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case PIPE_CAP_INVALIDATE_BUFFER:
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@ -60,9 +60,6 @@ struct brw_blorp_blit_vars {
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nir_variable *v_dst_offset;
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nir_variable *v_dst_offset;
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nir_variable *v_src_inv_size;
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nir_variable *v_src_inv_size;
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/* gl_FragCoord */
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nir_variable *frag_coord;
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/* gl_FragColor */
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/* gl_FragColor */
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nir_variable *color_out;
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nir_variable *color_out;
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};
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};
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@ -84,10 +81,6 @@ brw_blorp_blit_vars_init(nir_builder *b, struct brw_blorp_blit_vars *v,
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#undef LOAD_INPUT
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#undef LOAD_INPUT
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v->frag_coord = nir_variable_create(b->shader, nir_var_shader_in,
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glsl_vec4_type(), "gl_FragCoord");
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v->frag_coord->data.location = VARYING_SLOT_POS;
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v->color_out = nir_variable_create(b->shader, nir_var_shader_out,
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v->color_out = nir_variable_create(b->shader, nir_var_shader_out,
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glsl_vec4_type(), "gl_FragColor");
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glsl_vec4_type(), "gl_FragColor");
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v->color_out->data.location = FRAG_RESULT_COLOR;
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v->color_out->data.location = FRAG_RESULT_COLOR;
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@ -98,7 +91,7 @@ blorp_blit_get_frag_coords(nir_builder *b,
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const struct brw_blorp_blit_prog_key *key,
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const struct brw_blorp_blit_prog_key *key,
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struct brw_blorp_blit_vars *v)
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struct brw_blorp_blit_vars *v)
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{
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{
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nir_ssa_def *coord = nir_f2i32(b, nir_load_var(b, v->frag_coord));
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nir_ssa_def *coord = nir_f2i32(b, nir_load_frag_coord(b));
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/* Account for destination surface intratile offset
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/* Account for destination surface intratile offset
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*
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*
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@ -70,12 +70,7 @@ blorp_params_get_clear_kernel(struct blorp_batch *batch,
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nir_ssa_def *color = nir_load_var(&b, v_color);
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nir_ssa_def *color = nir_load_var(&b, v_color);
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if (clear_rgb_as_red) {
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if (clear_rgb_as_red) {
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nir_variable *frag_coord =
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nir_ssa_def *pos = nir_f2i32(&b, nir_load_frag_coord(&b));
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nir_variable_create(b.shader, nir_var_shader_in,
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glsl_vec4_type(), "gl_FragCoord");
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frag_coord->data.location = VARYING_SLOT_POS;
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nir_ssa_def *pos = nir_f2i32(&b, nir_load_var(&b, frag_coord));
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nir_ssa_def *comp = nir_umod(&b, nir_channel(&b, pos, 0),
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nir_ssa_def *comp = nir_umod(&b, nir_channel(&b, pos, 0),
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nir_imm_int(&b, 3));
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nir_imm_int(&b, 3));
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nir_ssa_def *color_component =
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nir_ssa_def *color_component =
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@ -976,7 +971,7 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch,
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/* Do an MCS fetch and check if it is equal to the magic clear value */
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/* Do an MCS fetch and check if it is equal to the magic clear value */
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nir_ssa_def *mcs =
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nir_ssa_def *mcs =
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blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, blorp_nir_frag_coord(&b)),
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blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, nir_load_frag_coord(&b)),
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nir_load_layer_id(&b));
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nir_load_layer_id(&b));
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nir_ssa_def *is_clear =
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nir_ssa_def *is_clear =
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blorp_nir_mcs_is_clear_color(&b, mcs, blorp_key.num_samples);
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blorp_nir_mcs_is_clear_color(&b, mcs, blorp_key.num_samples);
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@ -36,18 +36,6 @@ blorp_nir_init_shader(nir_builder *b,
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b->shader->info.fs.origin_upper_left = true;
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b->shader->info.fs.origin_upper_left = true;
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}
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}
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static inline nir_ssa_def *
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blorp_nir_frag_coord(nir_builder *b)
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{
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nir_variable *frag_coord =
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nir_variable_create(b->shader, nir_var_shader_in,
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glsl_vec4_type(), "gl_FragCoord");
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frag_coord->data.location = VARYING_SLOT_POS;
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return nir_load_var(b, frag_coord);
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}
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static inline nir_ssa_def *
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static inline nir_ssa_def *
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blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *xy_pos, nir_ssa_def *layer)
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blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *xy_pos, nir_ssa_def *layer)
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{
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{
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@ -6822,7 +6822,7 @@ fs_visitor::setup_fs_payload_gen6()
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assert(devinfo->gen >= 6);
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assert(devinfo->gen >= 6);
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prog_data->uses_src_depth = prog_data->uses_src_w =
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prog_data->uses_src_depth = prog_data->uses_src_w =
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(nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
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(nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) != 0;
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prog_data->uses_sample_mask =
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prog_data->uses_sample_mask =
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(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
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(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
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@ -7601,6 +7601,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
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emit_shader_time_begin();
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emit_shader_time_begin();
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if (nir->info.inputs_read > 0 ||
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if (nir->info.inputs_read > 0 ||
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(nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) ||
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(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
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(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
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if (devinfo->gen < 6)
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if (devinfo->gen < 6)
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emit_interpolation_setup_gen4();
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emit_interpolation_setup_gen4();
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@ -7707,10 +7708,7 @@ is_used_in_not_interp_frag_coord(nir_ssa_def *def)
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return true;
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return true;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src->parent_instr);
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src->parent_instr);
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if (intrin->intrinsic != nir_intrinsic_load_interpolated_input)
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if (intrin->intrinsic != nir_intrinsic_load_frag_coord)
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return true;
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if (nir_intrinsic_base(intrin) != VARYING_SLOT_POS)
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return true;
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return true;
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}
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}
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@ -3829,12 +3829,11 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
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break;
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break;
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}
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}
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case nir_intrinsic_load_interpolated_input: {
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case nir_intrinsic_load_frag_coord:
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if (nir_intrinsic_base(instr) == VARYING_SLOT_POS) {
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emit_fragcoord_interpolation(dest);
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emit_fragcoord_interpolation(dest);
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break;
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break;
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}
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case nir_intrinsic_load_interpolated_input: {
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assert(instr->src[0].ssa &&
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assert(instr->src[0].ssa &&
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instr->src[0].ssa->parent_instr->type == nir_instr_type_intrinsic);
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instr->src[0].ssa->parent_instr->type == nir_instr_type_intrinsic);
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nir_intrinsic_instr *bary_intrinsic =
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nir_intrinsic_instr *bary_intrinsic =
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@ -145,7 +145,7 @@ void fs_visitor::setup_fs_payload_gen4()
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payload.subspan_coord_reg[0] = reg++;
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payload.subspan_coord_reg[0] = reg++;
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prog_data->uses_src_depth =
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prog_data->uses_src_depth =
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(nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
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(nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) != 0;
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if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
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if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
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kill_stats_promoted_workaround) {
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kill_stats_promoted_workaround) {
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payload.source_depth_reg[0] = reg;
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payload.source_depth_reg[0] = reg;
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@ -167,6 +167,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
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};
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};
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struct spirv_to_nir_options spirv_options = {
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struct spirv_to_nir_options spirv_options = {
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.lower_workgroup_access_to_offsets = true,
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.lower_workgroup_access_to_offsets = true,
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.frag_coord_is_sysval = true,
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.caps = {
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.caps = {
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.demote_to_helper_invocation = true,
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.demote_to_helper_invocation = true,
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.derivative_group = true,
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.derivative_group = true,
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@ -652,7 +653,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
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if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
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NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
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NIR_PASS_V(nir, nir_lower_input_attachments, false);
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NIR_PASS_V(nir, nir_lower_input_attachments, true);
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}
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}
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NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
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NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
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@ -621,6 +621,7 @@ brw_initialize_context_constants(struct brw_context *brw)
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if (devinfo->gen >= 5 || devinfo->is_g4x)
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if (devinfo->gen >= 5 || devinfo->is_g4x)
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ctx->Const.MaxClipPlanes = 8;
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ctx->Const.MaxClipPlanes = 8;
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ctx->Const.GLSLFragCoordIsSysVal = true;
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ctx->Const.GLSLTessLevelsAsInputs = true;
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ctx->Const.GLSLTessLevelsAsInputs = true;
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ctx->Const.PrimitiveRestartForPatches = true;
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ctx->Const.PrimitiveRestartForPatches = true;
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@ -262,6 +262,7 @@ brwProgramStringNotify(struct gl_context *ctx,
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if (newFP == curFP)
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if (newFP == curFP)
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brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
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brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
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_mesa_program_fragment_position_to_sysval(&newFP->program);
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newFP->id = get_new_program_id(brw->screen);
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newFP->id = get_new_program_id(brw->screen);
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prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_FRAGMENT, true);
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prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_FRAGMENT, true);
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