anv/gen7: Disable fs dispatch for depth/stencil only pipelines
292031a for gen7
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>This commit is contained in:
Jordan Justen
parent
f5b3a2fe32
commit
4bb1e7937a
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@ -381,64 +381,70 @@ genX(graphics_pipeline_create)(
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.GSEnable = true);
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}
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const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
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if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
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wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
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anv_finishme("two-sided color needs sbe swizzling setup");
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if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
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anv_finishme("primitive_id needs sbe swizzling setup");
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if (pipeline->ps_ksp0 == NO_KERNEL) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));
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anv_finishme("gen7 alternative to "
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"3DSTATE_PS_EXTRA.PixelShaderValid = false");
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} else {
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const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
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if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
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wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
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anv_finishme("two-sided color needs sbe swizzling setup");
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if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
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anv_finishme("primitive_id needs sbe swizzling setup");
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/* FIXME: generated header doesn't emit attr swizzle fields */
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
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.NumberofSFOutputAttributes = pipeline->wm_prog_data.num_varying_inputs,
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.VertexURBEntryReadLength = urb_length,
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.VertexURBEntryReadOffset = urb_offset,
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.PointSpriteTextureCoordinateOrigin = UPPERLEFT);
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/* FIXME: generated header doesn't emit attr swizzle fields */
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
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.NumberofSFOutputAttributes = pipeline->wm_prog_data.num_varying_inputs,
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.VertexURBEntryReadLength = urb_length,
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.VertexURBEntryReadOffset = urb_offset,
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.PointSpriteTextureCoordinateOrigin = UPPERLEFT);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
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.KernelStartPointer0 = pipeline->ps_ksp0,
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.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
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.PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
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.KernelStartPointer0 = pipeline->ps_ksp0,
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.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
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.PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
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.MaximumNumberofThreads = device->info.max_wm_threads - 1,
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.PushConstantEnable = wm_prog_data->base.nr_params > 0,
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.AttributeEnable = wm_prog_data->num_varying_inputs > 0,
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.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
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.MaximumNumberofThreads = device->info.max_wm_threads - 1,
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.PushConstantEnable = wm_prog_data->base.nr_params > 0,
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.AttributeEnable = wm_prog_data->num_varying_inputs > 0,
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.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
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.RenderTargetFastClearEnable = false,
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.DualSourceBlendEnable = false,
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.RenderTargetResolveEnable = false,
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.RenderTargetFastClearEnable = false,
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.DualSourceBlendEnable = false,
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.RenderTargetResolveEnable = false,
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.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
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POSOFFSET_SAMPLE : POSOFFSET_NONE,
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.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
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POSOFFSET_SAMPLE : POSOFFSET_NONE,
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._32PixelDispatchEnable = false,
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._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
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._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
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._32PixelDispatchEnable = false,
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._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
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._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
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.DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
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.DispatchGRFStartRegisterforConstantSetupData1 = 0,
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.DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
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.DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
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.DispatchGRFStartRegisterforConstantSetupData1 = 0,
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.DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
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#if 0
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/* Haswell requires the sample mask to be set in this packet as well as
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* in 3DSTATE_SAMPLE_MASK; the values should match. */
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/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
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/* Haswell requires the sample mask to be set in this packet as well as
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* in 3DSTATE_SAMPLE_MASK; the values should match. */
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/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
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#endif
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.KernelStartPointer1 = 0,
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.KernelStartPointer2 = pipeline->ps_ksp2);
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.KernelStartPointer1 = 0,
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.KernelStartPointer2 = pipeline->ps_ksp2);
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/* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
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.StatisticsEnable = true,
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.ThreadDispatchEnable = true,
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.LineEndCapAntialiasingRegionWidth = 0, /* 0.5 pixels */
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.LineAntialiasingRegionWidth = 1, /* 1.0 pixels */
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.EarlyDepthStencilControl = EDSC_NORMAL,
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.PointRasterizationRule = RASTRULE_UPPER_RIGHT,
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.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
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.BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes);
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/* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
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.StatisticsEnable = true,
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.ThreadDispatchEnable = true,
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.LineEndCapAntialiasingRegionWidth = 0, /* 0.5 pixels */
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.LineAntialiasingRegionWidth = 1, /* 1.0 pixels */
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.EarlyDepthStencilControl = EDSC_NORMAL,
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.PointRasterizationRule = RASTRULE_UPPER_RIGHT,
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.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
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.BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes);
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}
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*pPipeline = anv_pipeline_to_handle(pipeline);
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