radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
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@ -621,16 +621,6 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
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}
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}
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static inline void
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radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
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unsigned size)
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{
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if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
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si_cp_dma_prefetch(cmd_buffer, va, size);
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}
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static void
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radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
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struct radv_shader_variant *shader)
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@ -645,22 +635,24 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
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va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
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radv_cs_add_buffer(ws, cs, shader->bo, 8);
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radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
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si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
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}
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static void
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radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
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struct radv_pipeline *pipeline)
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radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
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struct radv_pipeline *pipeline)
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{
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struct radv_cmd_state *state = &cmd_buffer->state;
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if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK)
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return;
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if (state->prefetch_L2_mask & RADV_PREFETCH_VS)
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radv_emit_shader_prefetch(cmd_buffer,
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pipeline->shaders[MESA_SHADER_VERTEX]);
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if (state->prefetch_L2_mask & RADV_PREFETCH_VBO_DESCRIPTORS)
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radv_emit_prefetch_TC_L2_async(cmd_buffer, state->vb_va,
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state->vb_size);
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si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
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if (state->prefetch_L2_mask & RADV_PREFETCH_TCS)
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radv_emit_shader_prefetch(cmd_buffer,
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@ -3077,8 +3069,8 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
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* important.
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*/
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if (cmd_buffer->state.prefetch_L2_mask) {
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radv_emit_prefetch(cmd_buffer,
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cmd_buffer->state.pipeline);
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radv_emit_prefetch_L2(cmd_buffer,
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cmd_buffer->state.pipeline);
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}
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} else {
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/* If we don't wait for idle, start prefetches first, then set
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@ -3087,8 +3079,8 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
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si_emit_cache_flush(cmd_buffer);
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if (cmd_buffer->state.prefetch_L2_mask) {
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radv_emit_prefetch(cmd_buffer,
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cmd_buffer->state.pipeline);
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radv_emit_prefetch_L2(cmd_buffer,
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cmd_buffer->state.pipeline);
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}
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if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
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